Lines Matching refs:regval
252 u32 regval; in get_ce_error_info() local
259 regval = readl(ddrmc_base + ECCR0_CE_ADDR_LO_OFFSET); in get_ce_error_info()
260 reghi = regval & ECCR_UE_CE_ADDR_HI_ROW_MASK; in get_ce_error_info()
261 p->ceinfo[0].i = regval | reghi << 32; in get_ce_error_info()
262 regval = readl(ddrmc_base + ECCR0_CE_ADDR_HI_OFFSET); in get_ce_error_info()
269 regval = readl(ddrmc_base + ECCR1_CE_ADDR_LO_OFFSET); in get_ce_error_info()
271 p->ceinfo[1].i = regval | reghi << 32; in get_ce_error_info()
272 regval = readl(ddrmc_base + ECCR1_CE_ADDR_HI_OFFSET); in get_ce_error_info()
284 u32 regval; in get_ue_error_info() local
291 regval = readl(ddrmc_base + ECCR0_UE_ADDR_LO_OFFSET); in get_ue_error_info()
294 p->ueinfo[0].i = regval | reghi << 32; in get_ue_error_info()
295 regval = readl(ddrmc_base + ECCR0_UE_ADDR_HI_OFFSET); in get_ue_error_info()
302 regval = readl(ddrmc_base + ECCR1_UE_ADDR_LO_OFFSET); in get_ue_error_info()
304 p->ueinfo[1].i = regval | reghi << 32; in get_ue_error_info()
460 int regval; in err_callback() local
465 regval = readl(priv->ddrmc_baseaddr + XDDR_ISR_OFFSET); in err_callback()
481 writel(regval, priv->ddrmc_baseaddr + XDDR_ISR_OFFSET); in err_callback()
501 u32 regval; in get_dwidth() local
504 regval = readl(base + XDDR_REG_CONFIG0_OFFSET); in get_dwidth()
505 width = FIELD_GET(XDDR_REG_CONFIG0_BUS_WIDTH_MASK, regval); in get_dwidth()
555 u32 regval; in get_memsize() local
558 regval = readl(priv->ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET); in get_memsize()
559 regval = FIELD_GET(XDDR_REG_CONFIG0_SIZE_MASK, regval); in get_memsize()
561 switch (regval) { in get_memsize()
685 u32 index, regval; in poison_setup() local
726 regval = row & XDDR_NOC_ROW_MATCH_MASK; in poison_setup()
727 regval |= FIELD_PREP(XDDR_NOC_COL_MATCH_MASK, col); in poison_setup()
728 regval |= FIELD_PREP(XDDR_NOC_BANK_MATCH_MASK, bank); in poison_setup()
729 regval |= FIELD_PREP(XDDR_NOC_GRP_MATCH_MASK, grp); in poison_setup()
730 writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC14_OFFSET); in poison_setup()
732 regval = rank & XDDR_NOC_RANK_MATCH_MASK; in poison_setup()
733 regval |= FIELD_PREP(XDDR_NOC_LRANK_MATCH_MASK, lrank); in poison_setup()
734 regval |= FIELD_PREP(XDDR_NOC_CH_MATCH_MASK, ch); in poison_setup()
735 regval |= (XDDR_NOC_MOD_SEL_MASK | XDDR_NOC_MATCH_EN_MASK); in poison_setup()
736 writel(regval, priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC15_OFFSET); in poison_setup()
937 static inline void process_bit(struct edac_priv *priv, unsigned int start, u32 regval) in process_bit() argument
941 rows.i = regval; in process_bit()
951 u32 regval; in setup_row_address_map() local
954 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC5_OFFSET); in setup_row_address_map()
955 process_bit(priv, 0, regval); in setup_row_address_map()
957 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC6_OFFSET); in setup_row_address_map()
958 process_bit(priv, 5, regval); in setup_row_address_map()
960 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC7_OFFSET); in setup_row_address_map()
961 process_bit(priv, 10, regval); in setup_row_address_map()
963 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC8_OFFSET); in setup_row_address_map()
964 rows.i = regval; in setup_row_address_map()
973 u32 regval; in setup_column_address_map() local
976 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC8_OFFSET); in setup_column_address_map()
977 priv->col_bit[0] = FIELD_GET(MASK_24, regval); in setup_column_address_map()
979 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC9_OFFSET); in setup_column_address_map()
980 cols.i = regval; in setup_column_address_map()
987 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC10_OFFSET); in setup_column_address_map()
988 cols.i = regval; in setup_column_address_map()
997 u32 regval; in setup_bank_grp_ch_address_map() local
999 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC10_OFFSET); in setup_bank_grp_ch_address_map()
1000 priv->bank_bit[0] = FIELD_GET(MASK_24, regval); in setup_bank_grp_ch_address_map()
1002 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC11_OFFSET); in setup_bank_grp_ch_address_map()
1003 priv->bank_bit[1] = (regval & MASK_0); in setup_bank_grp_ch_address_map()
1004 priv->grp_bit[0] = FIELD_GET(GRP_0_MASK, regval); in setup_bank_grp_ch_address_map()
1005 priv->grp_bit[1] = FIELD_GET(GRP_1_MASK, regval); in setup_bank_grp_ch_address_map()
1006 priv->ch_bit = FIELD_GET(CH_0_MASK, regval); in setup_bank_grp_ch_address_map()
1011 u32 regval; in setup_rank_lrank_address_map() local
1013 regval = readl(priv->ddrmc_noc_baseaddr + XDDR_NOC_REG_ADEC4_OFFSET); in setup_rank_lrank_address_map()
1014 priv->rank_bit[0] = (regval & MASK_0); in setup_rank_lrank_address_map()
1015 priv->rank_bit[1] = FIELD_GET(RANK_1_MASK, regval); in setup_rank_lrank_address_map()
1016 priv->lrank_bit[0] = FIELD_GET(LRANK_0_MASK, regval); in setup_rank_lrank_address_map()
1017 priv->lrank_bit[1] = FIELD_GET(LRANK_1_MASK, regval); in setup_rank_lrank_address_map()
1018 priv->lrank_bit[2] = FIELD_GET(MASK_24, regval); in setup_rank_lrank_address_map()
1083 u32 edac_mc_id, regval; in mc_probe() local
1100 regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET); in mc_probe()
1101 num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval); in mc_probe()
1104 num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval); in mc_probe()