Lines Matching refs:afb
726 static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb) in convert_tiling_flags_to_modifier_gfx12() argument
729 int swizzle_mode = AMDGPU_TILING_GET(afb->tiling_flags, GFX12_SWIZZLE_MODE); in convert_tiling_flags_to_modifier_gfx12()
735 AMDGPU_TILING_GET(afb->tiling_flags, GFX12_DCC_MAX_COMPRESSED_BLOCK); in convert_tiling_flags_to_modifier_gfx12()
741 AMD_FMT_MOD_SET(DCC, afb->gfx12_dcc) | in convert_tiling_flags_to_modifier_gfx12()
745 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier_gfx12()
746 afb->base.flags |= DRM_MODE_FB_MODIFIERS; in convert_tiling_flags_to_modifier_gfx12()
750 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) in convert_tiling_flags_to_modifier() argument
752 struct amdgpu_device *adev = drm_to_adev(afb->base.dev); in convert_tiling_flags_to_modifier()
760 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { in convert_tiling_flags_to_modifier()
763 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); in convert_tiling_flags_to_modifier()
772 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); in convert_tiling_flags_to_modifier()
819 if (!has_xor && afb->base.format->cpp[0] != 4) in convert_tiling_flags_to_modifier()
858 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | in convert_tiling_flags_to_modifier()
865 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; in convert_tiling_flags_to_modifier()
888 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0]; in convert_tiling_flags_to_modifier()
889 afb->base.pitches[1] = in convert_tiling_flags_to_modifier()
890 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; in convert_tiling_flags_to_modifier()
900 if (extract_render_dcc_offset(adev, afb->base.obj[0], in convert_tiling_flags_to_modifier()
903 render_dcc_offset != afb->base.offsets[1] && in convert_tiling_flags_to_modifier()
908 afb->base.offsets[2] = render_dcc_offset; in convert_tiling_flags_to_modifier()
926 dcc_block_bits -= ilog2(afb->base.format->cpp[0]); in convert_tiling_flags_to_modifier()
927 afb->base.pitches[2] = ALIGN(afb->base.width, in convert_tiling_flags_to_modifier()
930 format_info = amdgpu_lookup_format_info(afb->base.format->format, in convert_tiling_flags_to_modifier()
935 afb->base.format = format_info; in convert_tiling_flags_to_modifier()
939 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier()
940 afb->base.flags |= DRM_MODE_FB_MODIFIERS; in convert_tiling_flags_to_modifier()
945 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) in check_tiling_flags_gfx6() argument
949 if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */ in check_tiling_flags_gfx6()
952 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE); in check_tiling_flags_gfx6()
958 drm_dbg_kms(afb->base.dev, in check_tiling_flags_gfx6()