Lines Matching refs:modifier
653 amdgpu_lookup_format_info(u32 format, uint64_t modifier) in amdgpu_lookup_format_info() argument
655 if (!IS_AMD_FMT_MOD(modifier)) in amdgpu_lookup_format_info()
658 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) < AMD_FMT_MOD_TILE_VER_GFX9 || in amdgpu_lookup_format_info()
659 AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) in amdgpu_lookup_format_info()
662 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) in amdgpu_lookup_format_info()
667 if (AMD_FMT_MOD_GET(DCC, modifier)) in amdgpu_lookup_format_info()
728 u64 modifier = 0; in convert_tiling_flags_to_modifier_gfx12() local
732 modifier = DRM_FORMAT_MOD_LINEAR; in convert_tiling_flags_to_modifier_gfx12()
737 modifier = in convert_tiling_flags_to_modifier_gfx12()
745 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier_gfx12()
753 uint64_t modifier = 0; in convert_tiling_flags_to_modifier() local
761 modifier = DRM_FORMAT_MOD_LINEAR; in convert_tiling_flags_to_modifier()
857 modifier = AMD_FMT_MOD | in convert_tiling_flags_to_modifier()
882 modifier |= AMD_FMT_MOD_SET(DCC, 1) | in convert_tiling_flags_to_modifier()
907 modifier |= AMD_FMT_MOD_SET(DCC_RETILE, 1); in convert_tiling_flags_to_modifier()
921 modifier |= AMD_FMT_MOD_SET(RB, rb) | in convert_tiling_flags_to_modifier()
931 modifier); in convert_tiling_flags_to_modifier()
939 afb->base.modifier = modifier; in convert_tiling_flags_to_modifier()
977 static unsigned int get_dcc_block_size(uint64_t modifier, bool rb_aligned, in get_dcc_block_size() argument
980 unsigned int ver = AMD_FMT_MOD_GET(TILE_VERSION, modifier); in get_dcc_block_size()
989 return max(10 + (rb_aligned ? (int)AMD_FMT_MOD_GET(RB, modifier) : 0), 12); in get_dcc_block_size()
994 int pipes_log2 = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); in get_dcc_block_size()
997 AMD_FMT_MOD_GET(PACKERS, modifier) == pipes_log2) in get_dcc_block_size()
1061 uint64_t modifier = rfb->base.modifier; in amdgpu_display_verify_sizes() local
1069 if (modifier == DRM_FORMAT_MOD_LINEAR) { in amdgpu_display_verify_sizes()
1073 } else if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) >= AMD_FMT_MOD_TILE_VER_GFX12) { in amdgpu_display_verify_sizes()
1074 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes()
1098 int swizzle = AMD_FMT_MOD_GET(TILE, modifier); in amdgpu_display_verify_sizes()
1132 if (AMD_FMT_MOD_GET(TILE_VERSION, modifier) <= AMD_FMT_MOD_TILE_VER_GFX11 && in amdgpu_display_verify_sizes()
1133 AMD_FMT_MOD_GET(DCC, modifier)) { in amdgpu_display_verify_sizes()
1134 if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) { in amdgpu_display_verify_sizes()
1135 block_size_log2 = get_dcc_block_size(modifier, false, false); in amdgpu_display_verify_sizes()
1145 block_size_log2 = get_dcc_block_size(modifier, true, true); in amdgpu_display_verify_sizes()
1147 bool pipe_aligned = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); in amdgpu_display_verify_sizes()
1149 block_size_log2 = get_dcc_block_size(modifier, true, pipe_aligned); in amdgpu_display_verify_sizes()
1207 mode_cmd->modifier[0])) { in amdgpu_display_gem_fb_verify_and_init()
1210 &mode_cmd->pixel_format, mode_cmd->modifier[0]); in amdgpu_display_gem_fb_verify_and_init()