Lines Matching refs:op_input
922 struct mes_misc_op_input op_input; in amdgpu_mes_rreg() local
925 op_input.op = MES_MISC_OP_READ_REG; in amdgpu_mes_rreg()
926 op_input.read_reg.reg_offset = reg; in amdgpu_mes_rreg()
927 op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr; in amdgpu_mes_rreg()
934 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_rreg()
947 struct mes_misc_op_input op_input; in amdgpu_mes_wreg() local
950 op_input.op = MES_MISC_OP_WRITE_REG; in amdgpu_mes_wreg()
951 op_input.write_reg.reg_offset = reg; in amdgpu_mes_wreg()
952 op_input.write_reg.reg_value = val; in amdgpu_mes_wreg()
960 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_wreg()
972 struct mes_misc_op_input op_input; in amdgpu_mes_reg_write_reg_wait() local
975 op_input.op = MES_MISC_OP_WRM_REG_WR_WAIT; in amdgpu_mes_reg_write_reg_wait()
976 op_input.wrm_reg.reg0 = reg0; in amdgpu_mes_reg_write_reg_wait()
977 op_input.wrm_reg.reg1 = reg1; in amdgpu_mes_reg_write_reg_wait()
978 op_input.wrm_reg.ref = ref; in amdgpu_mes_reg_write_reg_wait()
979 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_write_reg_wait()
987 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_reg_write_reg_wait()
998 struct mes_misc_op_input op_input; in amdgpu_mes_reg_wait() local
1001 op_input.op = MES_MISC_OP_WRM_REG_WAIT; in amdgpu_mes_reg_wait()
1002 op_input.wrm_reg.reg0 = reg; in amdgpu_mes_reg_wait()
1003 op_input.wrm_reg.ref = val; in amdgpu_mes_reg_wait()
1004 op_input.wrm_reg.mask = mask; in amdgpu_mes_reg_wait()
1012 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_reg_wait()
1027 struct mes_misc_op_input op_input = {0}; in amdgpu_mes_set_shader_debugger() local
1035 op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; in amdgpu_mes_set_shader_debugger()
1036 op_input.set_shader_debugger.process_context_addr = process_context_addr; in amdgpu_mes_set_shader_debugger()
1037 op_input.set_shader_debugger.flags.u32all = flags; in amdgpu_mes_set_shader_debugger()
1040 if (op_input.set_shader_debugger.flags.process_ctx_flush) in amdgpu_mes_set_shader_debugger()
1043 op_input.set_shader_debugger.spi_gdbg_per_vmid_cntl = spi_gdbg_per_vmid_cntl; in amdgpu_mes_set_shader_debugger()
1044 memcpy(op_input.set_shader_debugger.tcp_watch_cntl, tcp_watch_cntl, in amdgpu_mes_set_shader_debugger()
1045 sizeof(op_input.set_shader_debugger.tcp_watch_cntl)); in amdgpu_mes_set_shader_debugger()
1049 op_input.set_shader_debugger.trap_en = trap_en; in amdgpu_mes_set_shader_debugger()
1053 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_set_shader_debugger()
1065 struct mes_misc_op_input op_input = {0}; in amdgpu_mes_flush_shader_debugger() local
1073 op_input.op = MES_MISC_OP_SET_SHADER_DEBUGGER; in amdgpu_mes_flush_shader_debugger()
1074 op_input.set_shader_debugger.process_context_addr = process_context_addr; in amdgpu_mes_flush_shader_debugger()
1075 op_input.set_shader_debugger.flags.process_ctx_flush = true; in amdgpu_mes_flush_shader_debugger()
1079 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_flush_shader_debugger()