Lines Matching defs:amdgpu_mes
64 struct amdgpu_mes { struct
65 struct amdgpu_device *adev;
67 struct mutex mutex_hidden;
69 struct idr pasid_idr;
70 struct idr gang_id_idr;
71 struct idr queue_id_idr;
72 struct ida doorbell_ida;
74 spinlock_t queue_id_lock;
76 uint32_t sched_version;
77 uint32_t kiq_version;
78 bool enable_legacy_queue_map;
80 uint32_t total_max_queue;
81 uint32_t max_doorbell_slices;
83 uint64_t default_process_quantum;
84 uint64_t default_gang_quantum;
86 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES];
87 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES];
89 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
92 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
93 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
94 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES];
99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
101 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
104 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
105 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
107 void *mqd_backup[AMDGPU_MAX_MES_PIPES];
108 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES];
110 uint32_t vmid_mask_gfxhub;
111 uint32_t vmid_mask_mmhub;
112 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
113 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
114 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
115 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
116 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES];
117 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES];
118 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES];
119 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES];
120 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES];
144 const struct amdgpu_mes_funcs *funcs; argument
153 struct amdgpu_mes_process { argument