Lines Matching refs:DRM_DEBUG
35 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); in amdgpu_ucode_print_common_hdr()
36 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); in amdgpu_ucode_print_common_hdr()
37 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); in amdgpu_ucode_print_common_hdr()
38 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); in amdgpu_ucode_print_common_hdr()
39 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); in amdgpu_ucode_print_common_hdr()
40 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); in amdgpu_ucode_print_common_hdr()
41 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); in amdgpu_ucode_print_common_hdr()
42 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); in amdgpu_ucode_print_common_hdr()
43 DRM_DEBUG("ucode_array_offset_bytes: %u\n", in amdgpu_ucode_print_common_hdr()
45 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); in amdgpu_ucode_print_common_hdr()
53 DRM_DEBUG("MC\n"); in amdgpu_ucode_print_mc_hdr()
60 DRM_DEBUG("io_debug_size_bytes: %u\n", in amdgpu_ucode_print_mc_hdr()
62 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", in amdgpu_ucode_print_mc_hdr()
77 DRM_DEBUG("SMC\n"); in amdgpu_ucode_print_smc_hdr()
82 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(v1_0_hdr->ucode_start_addr)); in amdgpu_ucode_print_smc_hdr()
87 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_offset_bytes)); in amdgpu_ucode_print_smc_hdr()
88 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_0_hdr->ppt_size_bytes)); in amdgpu_ucode_print_smc_hdr()
92 DRM_DEBUG("pptable_count: %u\n", le32_to_cpu(v2_1_hdr->pptable_count)); in amdgpu_ucode_print_smc_hdr()
93 DRM_DEBUG("pptable_entry_offset: %u\n", le32_to_cpu(v2_1_hdr->pptable_entry_offset)); in amdgpu_ucode_print_smc_hdr()
109 DRM_DEBUG("GFX\n"); in amdgpu_ucode_print_gfx_hdr()
116 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_gfx_hdr()
118 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); in amdgpu_ucode_print_gfx_hdr()
119 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); in amdgpu_ucode_print_gfx_hdr()
124 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_gfx_hdr()
136 DRM_DEBUG("RLC\n"); in amdgpu_ucode_print_rlc_hdr()
143 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_rlc_hdr()
145 DRM_DEBUG("save_and_restore_offset: %u\n", in amdgpu_ucode_print_rlc_hdr()
147 DRM_DEBUG("clear_state_descriptor_offset: %u\n", in amdgpu_ucode_print_rlc_hdr()
149 DRM_DEBUG("avail_scratch_ram_locations: %u\n", in amdgpu_ucode_print_rlc_hdr()
151 DRM_DEBUG("master_pkt_description_offset: %u\n", in amdgpu_ucode_print_rlc_hdr()
168 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_rlc_hdr()
170 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); in amdgpu_ucode_print_rlc_hdr()
171 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); in amdgpu_ucode_print_rlc_hdr()
172 DRM_DEBUG("save_and_restore_offset: %u\n", in amdgpu_ucode_print_rlc_hdr()
174 DRM_DEBUG("clear_state_descriptor_offset: %u\n", in amdgpu_ucode_print_rlc_hdr()
176 DRM_DEBUG("avail_scratch_ram_locations: %u\n", in amdgpu_ucode_print_rlc_hdr()
178 DRM_DEBUG("reg_restore_list_size: %u\n", in amdgpu_ucode_print_rlc_hdr()
180 DRM_DEBUG("reg_list_format_start: %u\n", in amdgpu_ucode_print_rlc_hdr()
182 DRM_DEBUG("reg_list_format_separate_start: %u\n", in amdgpu_ucode_print_rlc_hdr()
184 DRM_DEBUG("starting_offsets_start: %u\n", in amdgpu_ucode_print_rlc_hdr()
186 DRM_DEBUG("reg_list_format_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
188 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
190 DRM_DEBUG("reg_list_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
192 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
194 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
196 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
198 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
200 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
205 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", in amdgpu_ucode_print_rlc_hdr()
207 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", in amdgpu_ucode_print_rlc_hdr()
209 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", in amdgpu_ucode_print_rlc_hdr()
211 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", in amdgpu_ucode_print_rlc_hdr()
213 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
215 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", in amdgpu_ucode_print_rlc_hdr()
217 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", in amdgpu_ucode_print_rlc_hdr()
219 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", in amdgpu_ucode_print_rlc_hdr()
221 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
223 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", in amdgpu_ucode_print_rlc_hdr()
225 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", in amdgpu_ucode_print_rlc_hdr()
227 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", in amdgpu_ucode_print_rlc_hdr()
229 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
234 DRM_DEBUG("rlc_iram_ucode_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
236 DRM_DEBUG("rlc_iram_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
238 DRM_DEBUG("rlc_dram_ucode_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
240 DRM_DEBUG("rlc_dram_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
245 DRM_DEBUG("rlcp_ucode_version: %u\n", in amdgpu_ucode_print_rlc_hdr()
247 DRM_DEBUG("rlcp_ucode_feature_version: %u\n", in amdgpu_ucode_print_rlc_hdr()
249 DRM_DEBUG("rlcp_ucode_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
251 DRM_DEBUG("rlcp_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
253 DRM_DEBUG("rlcv_ucode_version: %u\n", in amdgpu_ucode_print_rlc_hdr()
255 DRM_DEBUG("rlcv_ucode_feature_version: %u\n", in amdgpu_ucode_print_rlc_hdr()
257 DRM_DEBUG("rlcv_ucode_size_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
259 DRM_DEBUG("rlcv_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
264 DRM_DEBUG("global_tap_delays_ucode_size_bytes :%u\n", in amdgpu_ucode_print_rlc_hdr()
266 DRM_DEBUG("global_tap_delays_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
268 DRM_DEBUG("se0_tap_delays_ucode_size_bytes :%u\n", in amdgpu_ucode_print_rlc_hdr()
270 DRM_DEBUG("se0_tap_delays_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
272 DRM_DEBUG("se1_tap_delays_ucode_size_bytes :%u\n", in amdgpu_ucode_print_rlc_hdr()
274 DRM_DEBUG("se1_tap_delays_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
276 DRM_DEBUG("se2_tap_delays_ucode_size_bytes :%u\n", in amdgpu_ucode_print_rlc_hdr()
278 DRM_DEBUG("se2_tap_delays_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
280 DRM_DEBUG("se3_tap_delays_ucode_size_bytes :%u\n", in amdgpu_ucode_print_rlc_hdr()
282 DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n", in amdgpu_ucode_print_rlc_hdr()
299 DRM_DEBUG("SDMA\n"); in amdgpu_ucode_print_sdma_hdr()
306 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_sdma_hdr()
308 DRM_DEBUG("ucode_change_version: %u\n", in amdgpu_ucode_print_sdma_hdr()
310 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); in amdgpu_ucode_print_sdma_hdr()
311 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); in amdgpu_ucode_print_sdma_hdr()
315 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); in amdgpu_ucode_print_sdma_hdr()
321 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_sdma_hdr()
323 DRM_DEBUG("ctx_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_offset)); in amdgpu_ucode_print_sdma_hdr()
324 DRM_DEBUG("ctx_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctx_jt_size)); in amdgpu_ucode_print_sdma_hdr()
325 DRM_DEBUG("ctl_ucode_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_ucode_offset)); in amdgpu_ucode_print_sdma_hdr()
326 DRM_DEBUG("ctl_jt_offset: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_offset)); in amdgpu_ucode_print_sdma_hdr()
327 DRM_DEBUG("ctl_jt_size: %u\n", le32_to_cpu(sdma_hdr->ctl_jt_size)); in amdgpu_ucode_print_sdma_hdr()
332 DRM_DEBUG("ucode_reversion: %u\n", in amdgpu_ucode_print_sdma_hdr()
347 DRM_DEBUG("PSP\n"); in amdgpu_ucode_print_psp_hdr()
354 DRM_DEBUG("ucode_feature_version: %u\n", in amdgpu_ucode_print_psp_hdr()
356 DRM_DEBUG("sos_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
358 DRM_DEBUG("sos_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
363 DRM_DEBUG("toc_header_version: %u\n", in amdgpu_ucode_print_psp_hdr()
365 DRM_DEBUG("toc_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
367 DRM_DEBUG("toc_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
369 DRM_DEBUG("kdb_header_version: %u\n", in amdgpu_ucode_print_psp_hdr()
371 DRM_DEBUG("kdb_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
373 DRM_DEBUG("kdb_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
379 DRM_DEBUG("kdb_header_version: %u\n", in amdgpu_ucode_print_psp_hdr()
381 DRM_DEBUG("kdb_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
383 DRM_DEBUG("kdb_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
391 DRM_DEBUG("toc_header_version: %u\n", in amdgpu_ucode_print_psp_hdr()
393 DRM_DEBUG("toc_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
395 DRM_DEBUG("toc_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
397 DRM_DEBUG("kdb_header_version: %u\n", in amdgpu_ucode_print_psp_hdr()
399 DRM_DEBUG("kdb_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
401 DRM_DEBUG("kdb_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
403 DRM_DEBUG("spl_header_version: %u\n", in amdgpu_ucode_print_psp_hdr()
405 DRM_DEBUG("spl_offset_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
407 DRM_DEBUG("spl_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
417 DRM_DEBUG("psp_sos_version: %u\n", in amdgpu_ucode_print_psp_hdr()
419 DRM_DEBUG("psp_sos_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
423 DRM_DEBUG("psp_sys_drv_version: %u\n", in amdgpu_ucode_print_psp_hdr()
425 DRM_DEBUG("psp_sys_drv_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
429 DRM_DEBUG("psp_kdb_version: %u\n", in amdgpu_ucode_print_psp_hdr()
431 DRM_DEBUG("psp_kdb_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
435 DRM_DEBUG("psp_toc_version: %u\n", in amdgpu_ucode_print_psp_hdr()
437 DRM_DEBUG("psp_toc_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
441 DRM_DEBUG("psp_spl_version: %u\n", in amdgpu_ucode_print_psp_hdr()
443 DRM_DEBUG("psp_spl_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
447 DRM_DEBUG("psp_rl_version: %u\n", in amdgpu_ucode_print_psp_hdr()
449 DRM_DEBUG("psp_rl_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
453 DRM_DEBUG("psp_soc_drv_version: %u\n", in amdgpu_ucode_print_psp_hdr()
455 DRM_DEBUG("psp_soc_drv_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
459 DRM_DEBUG("psp_intf_drv_version: %u\n", in amdgpu_ucode_print_psp_hdr()
461 DRM_DEBUG("psp_intf_drv_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
465 DRM_DEBUG("psp_dbg_drv_version: %u\n", in amdgpu_ucode_print_psp_hdr()
467 DRM_DEBUG("psp_dbg_drv_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
471 DRM_DEBUG("psp_ras_drv_version: %u\n", in amdgpu_ucode_print_psp_hdr()
473 DRM_DEBUG("psp_ras_drv_size_bytes: %u\n", in amdgpu_ucode_print_psp_hdr()
477 DRM_DEBUG("Unsupported PSP fw type: %d\n", desc->fw_type); in amdgpu_ucode_print_psp_hdr()
492 DRM_DEBUG("GPU_INFO\n"); in amdgpu_ucode_print_gpu_info_hdr()
499 DRM_DEBUG("version_major: %u\n", in amdgpu_ucode_print_gpu_info_hdr()
501 DRM_DEBUG("version_minor: %u\n", in amdgpu_ucode_print_gpu_info_hdr()