Lines Matching refs:inst_idx
81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
83 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
85 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
88 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
93 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
95 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
97 ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
107 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
135 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \ argument
137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ argument
147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
150 VCN, GET_INST(VCN, inst_idx), \
156 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
158 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
163 #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
168 addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg); \
186 #define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ argument
189 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
192 VCN, GET_INST(VCN, inst_idx), \
198 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
200 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
325 int inst_idx, struct dpg_pause_state *new_state);
519 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,