Lines Matching refs:adev
47 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev) in amdgpu_virt_mmio_blocked() argument
55 void amdgpu_virt_init_setting(struct amdgpu_device *adev) in amdgpu_virt_init_setting() argument
57 struct drm_device *ddev = adev_to_drm(adev); in amdgpu_virt_init_setting()
60 if (adev->asic_type != CHIP_ALDEBARAN && in amdgpu_virt_init_setting()
61 adev->asic_type != CHIP_ARCTURUS && in amdgpu_virt_init_setting()
62 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { in amdgpu_virt_init_setting()
63 if (adev->mode_info.num_crtc == 0) in amdgpu_virt_init_setting()
64 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
65 adev->enable_virtual_display = true; in amdgpu_virt_init_setting()
68 adev->cg_flags = 0; in amdgpu_virt_init_setting()
69 adev->pg_flags = 0; in amdgpu_virt_init_setting()
83 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init) in amdgpu_virt_request_full_gpu() argument
85 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_request_full_gpu()
89 r = virt->ops->req_full_gpu(adev, init); in amdgpu_virt_request_full_gpu()
91 adev->no_hw_access = true; in amdgpu_virt_request_full_gpu()
95 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_request_full_gpu()
108 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init) in amdgpu_virt_release_full_gpu() argument
110 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_release_full_gpu()
114 r = virt->ops->rel_full_gpu(adev, init); in amdgpu_virt_release_full_gpu()
118 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_release_full_gpu()
129 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev) in amdgpu_virt_reset_gpu() argument
131 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_reset_gpu()
135 r = virt->ops->reset_gpu(adev); in amdgpu_virt_reset_gpu()
139 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_reset_gpu()
145 void amdgpu_virt_request_init_data(struct amdgpu_device *adev) in amdgpu_virt_request_init_data() argument
147 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_request_init_data()
150 virt->ops->req_init_data(adev); in amdgpu_virt_request_init_data()
152 if (adev->virt.req_init_data_ver > 0) in amdgpu_virt_request_init_data()
164 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev) in amdgpu_virt_ready_to_reset() argument
166 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ready_to_reset()
169 virt->ops->ready_to_reset(adev); in amdgpu_virt_ready_to_reset()
178 int amdgpu_virt_wait_reset(struct amdgpu_device *adev) in amdgpu_virt_wait_reset() argument
180 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_wait_reset()
185 return virt->ops->wait_reset(adev); in amdgpu_virt_wait_reset()
194 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev) in amdgpu_virt_alloc_mm_table() argument
198 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
201 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE, in amdgpu_virt_alloc_mm_table()
204 &adev->virt.mm_table.bo, in amdgpu_virt_alloc_mm_table()
205 &adev->virt.mm_table.gpu_addr, in amdgpu_virt_alloc_mm_table()
206 (void *)&adev->virt.mm_table.cpu_addr); in amdgpu_virt_alloc_mm_table()
212 memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE); in amdgpu_virt_alloc_mm_table()
214 adev->virt.mm_table.gpu_addr, in amdgpu_virt_alloc_mm_table()
215 adev->virt.mm_table.cpu_addr); in amdgpu_virt_alloc_mm_table()
224 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev) in amdgpu_virt_free_mm_table() argument
226 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
229 amdgpu_bo_free_kernel(&adev->virt.mm_table.bo, in amdgpu_virt_free_mm_table()
230 &adev->virt.mm_table.gpu_addr, in amdgpu_virt_free_mm_table()
231 (void *)&adev->virt.mm_table.cpu_addr); in amdgpu_virt_free_mm_table()
232 adev->virt.mm_table.gpu_addr = 0; in amdgpu_virt_free_mm_table()
241 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev) in amdgpu_virt_rcvd_ras_interrupt() argument
243 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_rcvd_ras_interrupt()
248 return virt->ops->rcvd_ras_intr(adev); in amdgpu_virt_rcvd_ras_interrupt()
272 static int amdgpu_virt_init_ras_err_handler_data(struct amdgpu_device *adev) in amdgpu_virt_init_ras_err_handler_data() argument
274 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_init_ras_err_handler_data()
312 static void amdgpu_virt_ras_release_bp(struct amdgpu_device *adev) in amdgpu_virt_ras_release_bp() argument
314 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_release_bp()
332 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev) in amdgpu_virt_release_ras_err_handler_data() argument
334 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_release_ras_err_handler_data()
342 amdgpu_virt_ras_release_bp(adev); in amdgpu_virt_release_ras_err_handler_data()
350 static void amdgpu_virt_ras_add_bps(struct amdgpu_device *adev, in amdgpu_virt_ras_add_bps() argument
353 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_add_bps()
363 static void amdgpu_virt_ras_reserve_bps(struct amdgpu_device *adev) in amdgpu_virt_ras_reserve_bps() argument
365 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_reserve_bps()
367 struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; in amdgpu_virt_ras_reserve_bps()
385 amdgpu_vram_mgr_reserve_range(&adev->mman.vram_mgr, in amdgpu_virt_ras_reserve_bps()
390 if (amdgpu_bo_create_kernel_at(adev, bp << AMDGPU_GPU_PAGE_SHIFT, in amdgpu_virt_ras_reserve_bps()
401 static bool amdgpu_virt_ras_check_bad_page(struct amdgpu_device *adev, in amdgpu_virt_ras_check_bad_page() argument
404 struct amdgpu_virt *virt = &adev->virt; in amdgpu_virt_ras_check_bad_page()
418 static void amdgpu_virt_add_bad_page(struct amdgpu_device *adev, in amdgpu_virt_add_bad_page() argument
426 if (adev->mman.fw_vram_usage_va) in amdgpu_virt_add_bad_page()
427 vram_usage_va = adev->mman.fw_vram_usage_va; in amdgpu_virt_add_bad_page()
429 vram_usage_va = adev->mman.drv_vram_usage_va; in amdgpu_virt_add_bad_page()
440 if (amdgpu_virt_ras_check_bad_page(adev, retired_page)) in amdgpu_virt_add_bad_page()
443 amdgpu_virt_ras_add_bps(adev, &bp, 1); in amdgpu_virt_add_bad_page()
445 amdgpu_virt_ras_reserve_bps(adev); in amdgpu_virt_add_bad_page()
450 static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) in amdgpu_virt_read_pf2vf_data() argument
452 struct amd_sriov_msg_pf2vf_info_header *pf2vf_info = adev->virt.fw_reserve.p_pf2vf; in amdgpu_virt_read_pf2vf_data()
459 if (adev->virt.fw_reserve.p_pf2vf == NULL) in amdgpu_virt_read_pf2vf_data()
463 dev_err(adev->dev, "invalid pf2vf message size: 0x%x\n", pf2vf_info->size); in amdgpu_virt_read_pf2vf_data()
471 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, in amdgpu_virt_read_pf2vf_data()
472 adev->virt.fw_reserve.checksum_key, checksum); in amdgpu_virt_read_pf2vf_data()
474 dev_err(adev->dev, in amdgpu_virt_read_pf2vf_data()
480 adev->virt.gim_feature = in amdgpu_virt_read_pf2vf_data()
487 adev->virt.fw_reserve.p_pf2vf, pf2vf_info->size, in amdgpu_virt_read_pf2vf_data()
490 dev_err(adev->dev, in amdgpu_virt_read_pf2vf_data()
496 adev->virt.vf2pf_update_interval_ms = in amdgpu_virt_read_pf2vf_data()
498 adev->virt.gim_feature = in amdgpu_virt_read_pf2vf_data()
500 adev->virt.reg_access = in amdgpu_virt_read_pf2vf_data()
503 adev->virt.decode_max_dimension_pixels = 0; in amdgpu_virt_read_pf2vf_data()
504 adev->virt.decode_max_frame_pixels = 0; in amdgpu_virt_read_pf2vf_data()
505 adev->virt.encode_max_dimension_pixels = 0; in amdgpu_virt_read_pf2vf_data()
506 adev->virt.encode_max_frame_pixels = 0; in amdgpu_virt_read_pf2vf_data()
507 adev->virt.is_mm_bw_enabled = false; in amdgpu_virt_read_pf2vf_data()
510 adev->virt.decode_max_dimension_pixels = max(tmp, adev->virt.decode_max_dimension_pixels); in amdgpu_virt_read_pf2vf_data()
513 adev->virt.decode_max_frame_pixels = max(tmp, adev->virt.decode_max_frame_pixels); in amdgpu_virt_read_pf2vf_data()
516 adev->virt.encode_max_dimension_pixels = max(tmp, adev->virt.encode_max_dimension_pixels); in amdgpu_virt_read_pf2vf_data()
519 adev->virt.encode_max_frame_pixels = max(tmp, adev->virt.encode_max_frame_pixels); in amdgpu_virt_read_pf2vf_data()
521 if ((adev->virt.decode_max_dimension_pixels > 0) || (adev->virt.encode_max_dimension_pixels > 0)) in amdgpu_virt_read_pf2vf_data()
522 adev->virt.is_mm_bw_enabled = true; in amdgpu_virt_read_pf2vf_data()
524 adev->unique_id = in amdgpu_virt_read_pf2vf_data()
528 dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); in amdgpu_virt_read_pf2vf_data()
533 if (adev->virt.vf2pf_update_interval_ms < 200 || adev->virt.vf2pf_update_interval_ms > 10000) in amdgpu_virt_read_pf2vf_data()
534 adev->virt.vf2pf_update_interval_ms = 2000; in amdgpu_virt_read_pf2vf_data()
539 static void amdgpu_virt_populate_vf2pf_ucode_info(struct amdgpu_device *adev) in amdgpu_virt_populate_vf2pf_ucode_info() argument
542 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; in amdgpu_virt_populate_vf2pf_ucode_info()
544 if (adev->virt.fw_reserve.p_vf2pf == NULL) in amdgpu_virt_populate_vf2pf_ucode_info()
547 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCE, adev->vce.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_UVD, adev->uvd.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MC, adev->gmc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
550 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
551 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
552 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
553 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
554 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
555 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
556 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
557 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
558 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
559 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SOS, adev->psp.sos.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
561 adev->psp.asd_context.bin_desc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
563 adev->psp.ras_context.context.bin_desc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
565 adev->psp.xgmi_context.context.bin_desc.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
566 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SMC, adev->pm.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
567 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA, adev->sdma.instance[0].fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
568 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_SDMA2, adev->sdma.instance[1].fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
569 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_VCN, adev->vcn.fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
570 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_DMCU, adev->dm.dmcu_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
573 static int amdgpu_virt_write_vf2pf_data(struct amdgpu_device *adev) in amdgpu_virt_write_vf2pf_data() argument
577 vf2pf_info = (struct amd_sriov_msg_vf2pf_info *) adev->virt.fw_reserve.p_vf2pf; in amdgpu_virt_write_vf2pf_data()
579 if (adev->virt.fw_reserve.p_vf2pf == NULL) in amdgpu_virt_write_vf2pf_data()
599 ttm_resource_manager_usage(&adev->mman.vram_mgr.manager) >> 20; in amdgpu_virt_write_vf2pf_data()
601 amdgpu_vram_mgr_vis_usage(&adev->mman.vram_mgr) >> 20; in amdgpu_virt_write_vf2pf_data()
602 vf2pf_info->fb_size = adev->gmc.real_vram_size >> 20; in amdgpu_virt_write_vf2pf_data()
603 vf2pf_info->fb_vis_size = adev->gmc.visible_vram_size >> 20; in amdgpu_virt_write_vf2pf_data()
605 amdgpu_virt_populate_vf2pf_ucode_info(adev); in amdgpu_virt_write_vf2pf_data()
613 vf2pf_info->dummy_page_addr = (uint64_t)adev->dummy_page_addr; in amdgpu_virt_write_vf2pf_data()
614 vf2pf_info->mes_info_addr = (uint64_t)adev->mes.resource_1_gpu_addr; in amdgpu_virt_write_vf2pf_data()
616 if (adev->mes.resource_1) { in amdgpu_virt_write_vf2pf_data()
617 vf2pf_info->mes_info_size = adev->mes.resource_1->tbo.base.size; in amdgpu_virt_write_vf2pf_data()
628 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, virt.vf2pf_work.work); in amdgpu_virt_update_vf2pf_work_item() local
631 ret = amdgpu_virt_read_pf2vf_data(adev); in amdgpu_virt_update_vf2pf_work_item()
633 adev->virt.vf2pf_update_retry_cnt++; in amdgpu_virt_update_vf2pf_work_item()
635 if ((amdgpu_virt_rcvd_ras_interrupt(adev) || in amdgpu_virt_update_vf2pf_work_item()
636 adev->virt.vf2pf_update_retry_cnt >= AMDGPU_VF2PF_UPDATE_MAX_RETRY_LIMIT) && in amdgpu_virt_update_vf2pf_work_item()
637 amdgpu_sriov_runtime(adev)) { in amdgpu_virt_update_vf2pf_work_item()
639 amdgpu_ras_set_fed(adev, true); in amdgpu_virt_update_vf2pf_work_item()
640 if (amdgpu_reset_domain_schedule(adev->reset_domain, in amdgpu_virt_update_vf2pf_work_item()
641 &adev->kfd.reset_work)) in amdgpu_virt_update_vf2pf_work_item()
644 dev_err(adev->dev, "Failed to queue work! at %s", __func__); in amdgpu_virt_update_vf2pf_work_item()
650 adev->virt.vf2pf_update_retry_cnt = 0; in amdgpu_virt_update_vf2pf_work_item()
651 amdgpu_virt_write_vf2pf_data(adev); in amdgpu_virt_update_vf2pf_work_item()
654 schedule_delayed_work(&(adev->virt.vf2pf_work), adev->virt.vf2pf_update_interval_ms); in amdgpu_virt_update_vf2pf_work_item()
657 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev) in amdgpu_virt_fini_data_exchange() argument
659 if (adev->virt.vf2pf_update_interval_ms != 0) { in amdgpu_virt_fini_data_exchange()
661 cancel_delayed_work_sync(&adev->virt.vf2pf_work); in amdgpu_virt_fini_data_exchange()
662 adev->virt.vf2pf_update_interval_ms = 0; in amdgpu_virt_fini_data_exchange()
666 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev) in amdgpu_virt_init_data_exchange() argument
668 adev->virt.fw_reserve.p_pf2vf = NULL; in amdgpu_virt_init_data_exchange()
669 adev->virt.fw_reserve.p_vf2pf = NULL; in amdgpu_virt_init_data_exchange()
670 adev->virt.vf2pf_update_interval_ms = 0; in amdgpu_virt_init_data_exchange()
671 adev->virt.vf2pf_update_retry_cnt = 0; in amdgpu_virt_init_data_exchange()
673 if (adev->mman.fw_vram_usage_va && adev->mman.drv_vram_usage_va) { in amdgpu_virt_init_data_exchange()
675 } else if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { in amdgpu_virt_init_data_exchange()
677 amdgpu_virt_exchange_data(adev); in amdgpu_virt_init_data_exchange()
679 INIT_DELAYED_WORK(&adev->virt.vf2pf_work, amdgpu_virt_update_vf2pf_work_item); in amdgpu_virt_init_data_exchange()
680 …schedule_delayed_work(&(adev->virt.vf2pf_work), msecs_to_jiffies(adev->virt.vf2pf_update_interval_… in amdgpu_virt_init_data_exchange()
681 } else if (adev->bios != NULL) { in amdgpu_virt_init_data_exchange()
683 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_init_data_exchange()
685 (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); in amdgpu_virt_init_data_exchange()
687 amdgpu_virt_read_pf2vf_data(adev); in amdgpu_virt_init_data_exchange()
692 void amdgpu_virt_exchange_data(struct amdgpu_device *adev) in amdgpu_virt_exchange_data() argument
698 if (adev->mman.fw_vram_usage_va || adev->mman.drv_vram_usage_va) { in amdgpu_virt_exchange_data()
699 if (adev->mman.fw_vram_usage_va) { in amdgpu_virt_exchange_data()
700 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_exchange_data()
702 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); in amdgpu_virt_exchange_data()
703 adev->virt.fw_reserve.p_vf2pf = in amdgpu_virt_exchange_data()
705 (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); in amdgpu_virt_exchange_data()
706 } else if (adev->mman.drv_vram_usage_va) { in amdgpu_virt_exchange_data()
707 adev->virt.fw_reserve.p_pf2vf = in amdgpu_virt_exchange_data()
709 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10)); in amdgpu_virt_exchange_data()
710 adev->virt.fw_reserve.p_vf2pf = in amdgpu_virt_exchange_data()
712 (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); in amdgpu_virt_exchange_data()
715 amdgpu_virt_read_pf2vf_data(adev); in amdgpu_virt_exchange_data()
716 amdgpu_virt_write_vf2pf_data(adev); in amdgpu_virt_exchange_data()
719 if (adev->virt.fw_reserve.p_pf2vf->version == 2) { in amdgpu_virt_exchange_data()
720 pf2vf_v2 = (struct amd_sriov_msg_pf2vf_info *)adev->virt.fw_reserve.p_pf2vf; in amdgpu_virt_exchange_data()
726 if (bp_block_size && !adev->virt.ras_init_done) in amdgpu_virt_exchange_data()
727 amdgpu_virt_init_ras_err_handler_data(adev); in amdgpu_virt_exchange_data()
729 if (adev->virt.ras_init_done) in amdgpu_virt_exchange_data()
730 amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size); in amdgpu_virt_exchange_data()
735 void amdgpu_detect_virtualization(struct amdgpu_device *adev) in amdgpu_detect_virtualization() argument
739 switch (adev->asic_type) { in amdgpu_detect_virtualization()
760 adev->virt.caps |= AMDGPU_SRIOV_CAPS_IS_VF; in amdgpu_detect_virtualization()
763 adev->virt.caps |= AMDGPU_SRIOV_CAPS_ENABLE_IOV; in amdgpu_detect_virtualization()
768 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; in amdgpu_detect_virtualization()
772 if (amdgpu_sriov_vf(adev)) { in amdgpu_detect_virtualization()
773 switch (adev->asic_type) { in amdgpu_detect_virtualization()
776 vi_set_virt_ops(adev); in amdgpu_detect_virtualization()
779 soc15_set_virt_ops(adev); in amdgpu_detect_virtualization()
785 amdgpu_virt_request_init_data(adev); in amdgpu_detect_virtualization()
790 soc15_set_virt_ops(adev); in amdgpu_detect_virtualization()
796 nv_set_virt_ops(adev); in amdgpu_detect_virtualization()
798 amdgpu_virt_request_init_data(adev); in amdgpu_detect_virtualization()
801 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); in amdgpu_detect_virtualization()
807 static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev) in amdgpu_virt_access_debugfs_is_mmio() argument
809 return amdgpu_sriov_is_debug(adev) ? true : false; in amdgpu_virt_access_debugfs_is_mmio()
812 static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev) in amdgpu_virt_access_debugfs_is_kiq() argument
814 return amdgpu_sriov_is_normal(adev) ? true : false; in amdgpu_virt_access_debugfs_is_kiq()
817 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev) in amdgpu_virt_enable_access_debugfs() argument
819 if (!amdgpu_sriov_vf(adev) || in amdgpu_virt_enable_access_debugfs()
820 amdgpu_virt_access_debugfs_is_kiq(adev)) in amdgpu_virt_enable_access_debugfs()
823 if (amdgpu_virt_access_debugfs_is_mmio(adev)) in amdgpu_virt_enable_access_debugfs()
824 adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_enable_access_debugfs()
831 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev) in amdgpu_virt_disable_access_debugfs() argument
833 if (amdgpu_sriov_vf(adev)) in amdgpu_virt_disable_access_debugfs()
834 adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME; in amdgpu_virt_disable_access_debugfs()
837 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev) in amdgpu_virt_get_sriov_vf_mode() argument
841 if (amdgpu_sriov_vf(adev)) { in amdgpu_virt_get_sriov_vf_mode()
842 if (amdgpu_sriov_is_pp_one_vf(adev)) in amdgpu_virt_get_sriov_vf_mode()
853 void amdgpu_virt_pre_reset(struct amdgpu_device *adev) in amdgpu_virt_pre_reset() argument
856 amdgpu_virt_fini_data_exchange(adev); in amdgpu_virt_pre_reset()
857 amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_FLR); in amdgpu_virt_pre_reset()
860 void amdgpu_virt_post_reset(struct amdgpu_device *adev) in amdgpu_virt_post_reset() argument
862 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) { in amdgpu_virt_post_reset()
866 adev->gfx.is_poweron = false; in amdgpu_virt_post_reset()
869 adev->mes.ring[0].sched.ready = false; in amdgpu_virt_post_reset()
872 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, uint32_t ucode_id) in amdgpu_virt_fw_load_skip_check() argument
874 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_virt_fw_load_skip_check()
937 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, in amdgpu_virt_update_sriov_video_codec() argument
943 if (!adev->virt.is_mm_bw_enabled) in amdgpu_virt_update_sriov_video_codec()
948 encode[i].max_width = adev->virt.encode_max_dimension_pixels; in amdgpu_virt_update_sriov_video_codec()
949 encode[i].max_pixels_per_frame = adev->virt.encode_max_frame_pixels; in amdgpu_virt_update_sriov_video_codec()
959 decode[i].max_width = adev->virt.decode_max_dimension_pixels; in amdgpu_virt_update_sriov_video_codec()
960 decode[i].max_pixels_per_frame = adev->virt.decode_max_frame_pixels; in amdgpu_virt_update_sriov_video_codec()
969 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, in amdgpu_virt_get_rlcg_reg_access_flag() argument
977 if (amdgpu_sriov_reg_indirect_gc(adev)) { in amdgpu_virt_get_rlcg_reg_access_flag()
990 if (amdgpu_sriov_reg_indirect_mmhub(adev) && in amdgpu_virt_get_rlcg_reg_access_flag()
1002 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id) in amdgpu_virt_rlcg_reg_rw() argument
1014 if (!adev->gfx.rlc.rlcg_reg_access_supported) { in amdgpu_virt_rlcg_reg_rw()
1015 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1020 if (adev->gfx.xcc_mask && (((1 << xcc_id) & adev->gfx.xcc_mask) == 0)) { in amdgpu_virt_rlcg_reg_rw()
1021 dev_err(adev->dev, "invalid xcc\n"); in amdgpu_virt_rlcg_reg_rw()
1025 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_virt_rlcg_reg_rw()
1028 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1029 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw()
1030 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw()
1031 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()
1032 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw()
1034 mutex_lock(&adev->virt.rlcg_reg_lock); in amdgpu_virt_rlcg_reg_rw()
1037 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; in amdgpu_virt_rlcg_reg_rw()
1043 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); in amdgpu_virt_rlcg_reg_rw()
1048 writel(v, ((void __iomem *)adev->rmmio) + (offset * 4)); in amdgpu_virt_rlcg_reg_rw()
1070 if (amdgpu_sriov_rlcg_error_report_enabled(adev)) { in amdgpu_virt_rlcg_reg_rw()
1072 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1075 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1078 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1081 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1085 dev_err(adev->dev, in amdgpu_virt_rlcg_reg_rw()
1093 mutex_unlock(&adev->virt.rlcg_reg_lock); in amdgpu_virt_rlcg_reg_rw()
1098 void amdgpu_sriov_wreg(struct amdgpu_device *adev, in amdgpu_sriov_wreg() argument
1104 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_sriov_wreg()
1107 if (!amdgpu_sriov_runtime(adev) && in amdgpu_sriov_wreg()
1108 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) { in amdgpu_sriov_wreg()
1109 amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag, xcc_id); in amdgpu_sriov_wreg()
1119 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, in amdgpu_sriov_rreg() argument
1124 if (amdgpu_device_skip_hw_access(adev)) in amdgpu_sriov_rreg()
1127 if (!amdgpu_sriov_runtime(adev) && in amdgpu_sriov_rreg()
1128 amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag)) in amdgpu_sriov_rreg()
1129 return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag, xcc_id); in amdgpu_sriov_rreg()
1137 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) in amdgpu_sriov_xnack_support() argument
1141 if (amdgpu_sriov_vf(adev) && in amdgpu_sriov_xnack_support()
1142 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2)) in amdgpu_sriov_xnack_support()