Lines Matching refs:adev
87 int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
88 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
89 int (*req_init_data)(struct amdgpu_device *adev);
90 int (*reset_gpu)(struct amdgpu_device *adev);
91 void (*ready_to_reset)(struct amdgpu_device *adev);
92 int (*wait_reset)(struct amdgpu_device *adev);
93 void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
95 void (*ras_poison_handler)(struct amdgpu_device *adev,
97 bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
283 #define amdgpu_sriov_enabled(adev) \ argument
284 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
286 #define amdgpu_sriov_vf(adev) \ argument
287 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
289 #define amdgpu_sriov_bios(adev) \ argument
290 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
292 #define amdgpu_sriov_runtime(adev) \ argument
293 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
295 #define amdgpu_sriov_fullaccess(adev) \ argument
296 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
298 #define amdgpu_sriov_reg_indirect_en(adev) \ argument
299 (amdgpu_sriov_vf((adev)) && \
300 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
302 #define amdgpu_sriov_reg_indirect_ih(adev) \ argument
303 (amdgpu_sriov_vf((adev)) && \
304 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
306 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ argument
307 (amdgpu_sriov_vf((adev)) && \
308 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
310 #define amdgpu_sriov_reg_indirect_gc(adev) \ argument
311 (amdgpu_sriov_vf((adev)) && \
312 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
314 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ argument
315 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
317 #define amdgpu_passthrough(adev) \ argument
318 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
320 #define amdgpu_sriov_vf_mmio_access_protection(adev) \ argument
321 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
334 #define amdgpu_sriov_is_pp_one_vf(adev) \ argument
335 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
336 #define amdgpu_sriov_is_debug(adev) \ argument
337 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
338 #define amdgpu_sriov_is_normal(adev) \ argument
339 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
340 #define amdgpu_sriov_is_av1_support(adev) \ argument
341 ((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
342 #define amdgpu_sriov_is_vcn_rb_decouple(adev) \ argument
343 ((adev)->virt.gim_feature & AMDGIM_FEATURE_VCN_RB_DECOUPLE)
344 #define amdgpu_sriov_is_mes_info_enable(adev) \ argument
345 ((adev)->virt.gim_feature & AMDGIM_FEATURE_MES_INFO_ENABLE)
346 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
347 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
348 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
349 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
350 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
351 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
352 void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev);
353 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
354 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
355 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
356 bool amdgpu_virt_rcvd_ras_interrupt(struct amdgpu_device *adev);
357 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
358 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
359 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
360 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
361 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
363 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
364 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
365 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
367 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
369 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
372 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
375 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
377 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
379 void amdgpu_virt_pre_reset(struct amdgpu_device *adev);
380 void amdgpu_virt_post_reset(struct amdgpu_device *adev);
381 bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev);
382 bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
385 u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id);