Lines Matching refs:dig
1214 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_audio_select_pin() local
1217 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_afmt_audio_select_pin()
1220 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1221 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1222 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_latency_fields() local
1238 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_latency_fields()
1268 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_latency_fields()
1277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_speaker_allocation() local
1285 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_speaker_allocation()
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_sad_regs() local
1355 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_sad_regs()
1408 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1488 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_ACR() local
1491 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1493 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1494 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1496 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1498 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1500 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1501 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1503 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1505 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1507 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1508 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1510 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1523 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_avi_infoframe() local
1527 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1529 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1531 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1533 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1542 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_set_dto() local
1548 if (!dig || !dig->afmt) in dce_v10_0_audio_set_dto()
1573 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_setmode() local
1581 if (!dig || !dig->afmt) in dce_v10_0_afmt_setmode()
1585 if (!dig->afmt->enabled) in dce_v10_0_afmt_setmode()
1595 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1596 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1600 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1602 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1604 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v10_0_afmt_setmode()
1606 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1631 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1633 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1637 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1639 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1644 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1646 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1649 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1651 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1654 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1656 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v10_0_afmt_setmode()
1658 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1663 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1665 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1668 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1670 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1679 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1683 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1685 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1687 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1689 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1691 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1698 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1702 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v10_0_afmt_setmode()
1723 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1728 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1730 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1732 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1734 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1737 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1739 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v10_0_afmt_setmode()
1740 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v10_0_afmt_setmode()
1741 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1742 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1745 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1753 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_enable() local
1755 if (!dig || !dig->afmt) in dce_v10_0_afmt_enable()
1759 if (enable && dig->afmt->enabled) in dce_v10_0_afmt_enable()
1761 if (!enable && !dig->afmt->enabled) in dce_v10_0_afmt_enable()
1764 if (!enable && dig->afmt->pin) { in dce_v10_0_afmt_enable()
1765 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1766 dig->afmt->pin = NULL; in dce_v10_0_afmt_enable()
1769 dig->afmt->enabled = enable; in dce_v10_0_afmt_enable()
1772 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v10_0_afmt_enable()
2195 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_pick_dig_encoder() local
2199 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2204 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2209 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
3373 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_prepare() local
3374 if (dig) { in dce_v10_0_encoder_prepare()
3375 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); in dce_v10_0_encoder_prepare()
3377 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()
3415 struct amdgpu_encoder_atom_dig *dig; in dce_v10_0_encoder_disable() local
3422 dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_disable()
3423 dig->dig_encoder = -1; in dce_v10_0_encoder_disable()