Lines Matching refs:hpd
55 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
90 uint32_t hpd; member
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
281 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_sense() argument
285 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_sense()
288 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & in dce_v10_0_hpd_sense()
304 enum amdgpu_hpd_id hpd) in dce_v10_0_hpd_set_polarity() argument
307 bool connected = dce_v10_0_hpd_sense(adev, hpd); in dce_v10_0_hpd_set_polarity()
309 if (hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_set_polarity()
312 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_set_polarity()
317 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_set_polarity()
339 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_init()
349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
355 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
357 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
359 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_init()
366 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_init()
368 dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
371 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_init()
395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) in dce_v10_0_hpd_fini()
398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); in dce_v10_0_hpd_fini()
400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); in dce_v10_0_hpd_fini()
403 amdgpu_connector->hpd.hpd); in dce_v10_0_hpd_fini()
3050 unsigned hpd, in dce_v10_0_set_hpd_irq_state() argument
3055 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_set_hpd_irq_state()
3056 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_set_hpd_irq_state()
3062 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3064 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3067 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_set_hpd_irq_state()
3069 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_set_hpd_irq_state()
3203 int hpd) in dce_v10_0_hpd_int_ack() argument
3207 if (hpd >= adev->mode_info.num_hpd) { in dce_v10_0_hpd_int_ack()
3208 DRM_DEBUG("invalid hdp %d\n", hpd); in dce_v10_0_hpd_int_ack()
3212 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); in dce_v10_0_hpd_int_ack()
3214 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); in dce_v10_0_hpd_int_ack()
3290 unsigned hpd; in dce_v10_0_hpd_irq() local
3297 hpd = entry->src_data[0]; in dce_v10_0_hpd_irq()
3298 disp_int = RREG32(interrupt_status_offsets[hpd].reg); in dce_v10_0_hpd_irq()
3299 mask = interrupt_status_offsets[hpd].hpd; in dce_v10_0_hpd_irq()
3302 dce_v10_0_hpd_int_ack(adev, hpd); in dce_v10_0_hpd_irq()
3304 DRM_DEBUG("IH: HPD%d\n", hpd + 1); in dce_v10_0_hpd_irq()