Lines Matching refs:wave
776 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) in wave_read_ind() argument
779 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_ind()
784 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, in wave_read_regs() argument
789 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | in wave_read_regs()
799 uint32_t simd, uint32_t wave, in gfx_v12_0_read_wave_data() argument
809 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); in gfx_v12_0_read_wave_data()
810 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); in gfx_v12_0_read_wave_data()
811 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); in gfx_v12_0_read_wave_data()
812 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); in gfx_v12_0_read_wave_data()
813 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); in gfx_v12_0_read_wave_data()
814 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); in gfx_v12_0_read_wave_data()
815 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); in gfx_v12_0_read_wave_data()
816 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); in gfx_v12_0_read_wave_data()
817 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); in gfx_v12_0_read_wave_data()
818 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); in gfx_v12_0_read_wave_data()
819 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); in gfx_v12_0_read_wave_data()
820 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); in gfx_v12_0_read_wave_data()
821 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); in gfx_v12_0_read_wave_data()
822 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); in gfx_v12_0_read_wave_data()
823 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATE_PRIV); in gfx_v12_0_read_wave_data()
824 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); in gfx_v12_0_read_wave_data()
825 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXCP_FLAG_USER); in gfx_v12_0_read_wave_data()
826 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAP_CTRL); in gfx_v12_0_read_wave_data()
827 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_ACTIVE); in gfx_v12_0_read_wave_data()
828 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_VALID_AND_IDLE); in gfx_v12_0_read_wave_data()
829 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); in gfx_v12_0_read_wave_data()
830 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); in gfx_v12_0_read_wave_data()
831 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_SCHED_MODE); in gfx_v12_0_read_wave_data()
836 uint32_t wave, uint32_t start, in gfx_v12_0_read_wave_sgprs() argument
842 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, in gfx_v12_0_read_wave_sgprs()
848 uint32_t wave, uint32_t thread, in gfx_v12_0_read_wave_vgprs() argument
853 adev, wave, thread, in gfx_v12_0_read_wave_vgprs()