Lines Matching refs:rlc
2485 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_cp_gfx_start()
3198 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3199 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3202 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; in gfx_v7_0_rlc_init()
3203 adev->gfx.rlc.reg_list_size = in gfx_v7_0_rlc_init()
3207 adev->gfx.rlc.cs_data = ci_cs_data; in gfx_v7_0_rlc_init()
3208 adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */ in gfx_v7_0_rlc_init()
3209 adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */ in gfx_v7_0_rlc_init()
3211 src_ptr = adev->gfx.rlc.reg_list; in gfx_v7_0_rlc_init()
3212 dws = adev->gfx.rlc.reg_list_size; in gfx_v7_0_rlc_init()
3215 cs_data = adev->gfx.rlc.cs_data; in gfx_v7_0_rlc_init()
3231 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_rlc_init()
3238 if (adev->gfx.rlc.funcs->update_spm_vmid) in gfx_v7_0_rlc_init()
3239 adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); in gfx_v7_0_rlc_init()
3286 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc) in gfx_v7_0_update_rlc() argument
3291 if (tmp != rlc) in gfx_v7_0_update_rlc()
3292 WREG32(mmRLC_CNTL, rlc); in gfx_v7_0_update_rlc()
3423 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_rlc_resume()
3429 adev->gfx.rlc.funcs->reset(adev); in gfx_v7_0_rlc_resume()
3460 adev->gfx.rlc.funcs->start(adev); in gfx_v7_0_rlc_resume()
3793 if (adev->gfx.rlc.cs_data) { in gfx_v7_0_init_gfx_cgpg()
3795 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3796 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); in gfx_v7_0_init_gfx_cgpg()
3797 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); in gfx_v7_0_init_gfx_cgpg()
3803 if (adev->gfx.rlc.reg_list) { in gfx_v7_0_init_gfx_cgpg()
3805 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) in gfx_v7_0_init_gfx_cgpg()
3806 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); in gfx_v7_0_init_gfx_cgpg()
3814 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3815 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); in gfx_v7_0_init_gfx_cgpg()
3850 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_size()
3858 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_size()
3883 if (adev->gfx.rlc.cs_data == NULL) in gfx_v7_0_get_csb_buffer()
3895 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { in gfx_v7_0_get_csb_buffer()
4146 adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs; in gfx_v7_0_early_init()
4390 r = adev->gfx.rlc.funcs->init(adev); in gfx_v7_0_sw_init()
4455 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, in gfx_v7_0_sw_fini()
4456 &adev->gfx.rlc.clear_state_gpu_addr, in gfx_v7_0_sw_fini()
4457 (void **)&adev->gfx.rlc.cs_ptr); in gfx_v7_0_sw_fini()
4458 if (adev->gfx.rlc.cp_table_size) { in gfx_v7_0_sw_fini()
4459 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, in gfx_v7_0_sw_fini()
4460 &adev->gfx.rlc.cp_table_gpu_addr, in gfx_v7_0_sw_fini()
4461 (void **)&adev->gfx.rlc.cp_table_ptr); in gfx_v7_0_sw_fini()
4476 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); in gfx_v7_0_hw_init()
4478 r = adev->gfx.rlc.funcs->resume(adev); in gfx_v7_0_hw_init()
4496 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_hw_fini()
4581 adev->gfx.rlc.funcs->stop(adev); in gfx_v7_0_soft_reset()