Lines Matching refs:ih
52 if (adev->irq.ih.ring_size) { in ih_v6_0_init_register_offset()
53 ih_regs = &adev->irq.ih.ih_regs; in ih_v6_0_init_register_offset()
128 struct amdgpu_ih_ring *ih, in ih_v6_0_toggle_ring_interrupts() argument
134 ih_regs = &ih->ih_regs; in ih_v6_0_toggle_ring_interrupts()
167 if (ih == &adev->irq.ih) in ih_v6_0_toggle_ring_interrupts()
178 ih->enabled = true; in ih_v6_0_toggle_ring_interrupts()
183 ih->enabled = false; in ih_v6_0_toggle_ring_interrupts()
184 ih->rptr = 0; in ih_v6_0_toggle_ring_interrupts()
200 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_toggle_interrupts() local
204 for (i = 0; i < ARRAY_SIZE(ih); i++) { in ih_v6_0_toggle_interrupts()
205 if (ih[i]->ring_size) { in ih_v6_0_toggle_interrupts()
206 r = ih_v6_0_toggle_ring_interrupts(adev, ih[i], enable); in ih_v6_0_toggle_interrupts()
215 static uint32_t ih_v6_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl) in ih_v6_0_rb_cntl() argument
217 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v6_0_rb_cntl()
220 MC_SPACE, ih->use_bus_addr ? 2 : 4); in ih_v6_0_rb_cntl()
238 static uint32_t ih_v6_0_doorbell_rptr(struct amdgpu_ih_ring *ih) in ih_v6_0_doorbell_rptr() argument
242 if (ih->use_doorbell) { in ih_v6_0_doorbell_rptr()
245 ih->doorbell_index); in ih_v6_0_doorbell_rptr()
266 struct amdgpu_ih_ring *ih) in ih_v6_0_enable_ring() argument
271 ih_regs = &ih->ih_regs; in ih_v6_0_enable_ring()
274 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8); in ih_v6_0_enable_ring()
275 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff); in ih_v6_0_enable_ring()
278 tmp = ih_v6_0_rb_cntl(ih, tmp); in ih_v6_0_enable_ring()
279 if (ih == &adev->irq.ih) in ih_v6_0_enable_ring()
281 if (ih == &adev->irq.ih1) { in ih_v6_0_enable_ring()
295 if (ih == &adev->irq.ih) { in ih_v6_0_enable_ring()
297 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr)); in ih_v6_0_enable_ring()
298 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF); in ih_v6_0_enable_ring()
305 WREG32(ih_regs->ih_doorbell_rptr, ih_v6_0_doorbell_rptr(ih)); in ih_v6_0_enable_ring()
323 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1}; in ih_v6_0_irq_init() local
338 if (ih[0]->use_bus_addr) { in ih_v6_0_irq_init()
346 for (i = 0; i < ARRAY_SIZE(ih); i++) { in ih_v6_0_irq_init()
347 if (ih[i]->ring_size) { in ih_v6_0_irq_init()
348 ret = ih_v6_0_enable_ring(adev, ih[i]); in ih_v6_0_irq_init()
355 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell, in ih_v6_0_irq_init()
356 ih[0]->doorbell_index); in ih_v6_0_irq_init()
435 struct amdgpu_ih_ring *ih) in ih_v6_0_get_wptr() argument
440 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_0_get_wptr()
441 ih_regs = &ih->ih_regs; in ih_v6_0_get_wptr()
455 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_0_get_wptr()
458 wptr, ih->rptr, tmp); in ih_v6_0_get_wptr()
459 ih->rptr = tmp; in ih_v6_0_get_wptr()
471 return (wptr & ih->ptr_mask); in ih_v6_0_get_wptr()
482 struct amdgpu_ih_ring *ih) in ih_v6_0_irq_rearm() argument
488 ih_regs = &ih->ih_regs; in ih_v6_0_irq_rearm()
493 if ((v < ih->ring_size) && (v != ih->rptr)) in ih_v6_0_irq_rearm()
494 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_irq_rearm()
509 struct amdgpu_ih_ring *ih) in ih_v6_0_set_rptr() argument
513 if (ih->use_doorbell) { in ih_v6_0_set_rptr()
515 *ih->rptr_cpu = ih->rptr; in ih_v6_0_set_rptr()
516 WDOORBELL32(ih->doorbell_index, ih->rptr); in ih_v6_0_set_rptr()
519 ih_v6_0_irq_rearm(adev, ih); in ih_v6_0_set_rptr()
521 ih_regs = &ih->ih_regs; in ih_v6_0_set_rptr()
522 WREG32(ih_regs->ih_rb_rptr, ih->rptr); in ih_v6_0_set_rptr()
588 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr); in ih_v6_0_sw_init()
592 adev->irq.ih.use_doorbell = true; in ih_v6_0_sw_init()
593 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1; in ih_v6_0_sw_init()
602 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1; in ih_v6_0_sw_init()