Lines Matching refs:mes
159 static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, in mes_v11_0_submit_pkt_and_poll_completion() argument
165 struct amdgpu_device *adev = mes->adev; in mes_v11_0_submit_pkt_and_poll_completion()
166 struct amdgpu_ring *ring = &mes->ring[0]; in mes_v11_0_submit_pkt_and_poll_completion()
195 spin_lock_irqsave(&mes->ring_lock[0], flags); in mes_v11_0_submit_pkt_and_poll_completion()
225 spin_unlock_irqrestore(&mes->ring_lock[0], flags); in mes_v11_0_submit_pkt_and_poll_completion()
267 spin_unlock_irqrestore(&mes->ring_lock[0], flags); in mes_v11_0_submit_pkt_and_poll_completion()
287 static int mes_v11_0_add_hw_queue(struct amdgpu_mes *mes, in mes_v11_0_add_hw_queue() argument
290 struct amdgpu_device *adev = mes->adev; in mes_v11_0_add_hw_queue()
316 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> in mes_v11_0_add_hw_queue()
340 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_add_hw_queue()
345 static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, in mes_v11_0_remove_hw_queue() argument
359 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_remove_hw_queue()
364 static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, in mes_v11_0_reset_queue_mmio() argument
368 struct amdgpu_device *adev = mes->adev; in mes_v11_0_reset_queue_mmio()
433 static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, in mes_v11_0_reset_hw_queue() argument
437 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, in mes_v11_0_reset_hw_queue()
453 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_reset_hw_queue()
458 static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, in mes_v11_0_map_legacy_queue() argument
478 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_map_legacy_queue()
483 static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, in mes_v11_0_unmap_legacy_queue() argument
511 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_unmap_legacy_queue()
516 static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, in mes_v11_0_suspend_gang() argument
532 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_suspend_gang()
537 static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, in mes_v11_0_resume_gang() argument
551 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_resume_gang()
556 static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) in mes_v11_0_query_sched_status() argument
566 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_query_sched_status()
571 static int mes_v11_0_misc_op(struct amdgpu_mes *mes, in mes_v11_0_misc_op() argument
627 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_misc_op()
632 static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) in mes_v11_0_set_hw_resources() argument
635 struct amdgpu_device *adev = mes->adev; in mes_v11_0_set_hw_resources()
644 mes_set_hw_res_pkt.vmid_mask_mmhub = mes->vmid_mask_mmhub; in mes_v11_0_set_hw_resources()
645 mes_set_hw_res_pkt.vmid_mask_gfxhub = mes->vmid_mask_gfxhub; in mes_v11_0_set_hw_resources()
648 mes_set_hw_res_pkt.g_sch_ctx_gpu_mc_ptr = mes->sch_ctx_gpu_addr[0]; in mes_v11_0_set_hw_resources()
650 mes->query_status_fence_gpu_addr[0]; in mes_v11_0_set_hw_resources()
654 mes->compute_hqd_mask[i]; in mes_v11_0_set_hw_resources()
657 mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; in mes_v11_0_set_hw_resources()
660 mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; in mes_v11_0_set_hw_resources()
664 mes->aggregated_doorbells[i]; in mes_v11_0_set_hw_resources()
683 mes->event_log_gpu_addr; in mes_v11_0_set_hw_resources()
686 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_set_hw_resources()
691 static int mes_v11_0_set_hw_resources_1(struct amdgpu_mes *mes) in mes_v11_0_set_hw_resources_1() argument
695 struct amdgpu_device *adev = mes->adev; in mes_v11_0_set_hw_resources_1()
706 &mes->resource_1, in mes_v11_0_set_hw_resources_1()
707 &mes->resource_1_gpu_addr, in mes_v11_0_set_hw_resources_1()
708 &mes->resource_1_addr); in mes_v11_0_set_hw_resources_1()
714 mes_set_hw_res_pkt.mes_info_ctx_mc_addr = mes->resource_1_gpu_addr; in mes_v11_0_set_hw_resources_1()
715 mes_set_hw_res_pkt.mes_info_ctx_size = mes->resource_1->tbo.base.size; in mes_v11_0_set_hw_resources_1()
716 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_set_hw_resources_1()
721 static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes, in mes_v11_0_reset_legacy_queue() argument
727 return mes_v11_0_reset_queue_mmio(mes, input->queue_type, in mes_v11_0_reset_legacy_queue()
753 return mes_v11_0_submit_pkt_and_poll_completion(mes, in mes_v11_0_reset_legacy_queue()
779 adev->mes.fw[pipe]->data; in mes_v11_0_allocate_ucode_buffer()
781 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v11_0_allocate_ucode_buffer()
789 &adev->mes.ucode_fw_obj[pipe], in mes_v11_0_allocate_ucode_buffer()
790 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v11_0_allocate_ucode_buffer()
791 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v11_0_allocate_ucode_buffer()
797 memcpy(adev->mes.ucode_fw_ptr[pipe], fw_data, fw_size); in mes_v11_0_allocate_ucode_buffer()
799 amdgpu_bo_kunmap(adev->mes.ucode_fw_obj[pipe]); in mes_v11_0_allocate_ucode_buffer()
800 amdgpu_bo_unreserve(adev->mes.ucode_fw_obj[pipe]); in mes_v11_0_allocate_ucode_buffer()
814 adev->mes.fw[pipe]->data; in mes_v11_0_allocate_ucode_data_buffer()
816 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + in mes_v11_0_allocate_ucode_data_buffer()
830 &adev->mes.data_fw_obj[pipe], in mes_v11_0_allocate_ucode_data_buffer()
831 &adev->mes.data_fw_gpu_addr[pipe], in mes_v11_0_allocate_ucode_data_buffer()
832 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v11_0_allocate_ucode_data_buffer()
838 memcpy(adev->mes.data_fw_ptr[pipe], fw_data, fw_size); in mes_v11_0_allocate_ucode_data_buffer()
840 amdgpu_bo_kunmap(adev->mes.data_fw_obj[pipe]); in mes_v11_0_allocate_ucode_data_buffer()
841 amdgpu_bo_unreserve(adev->mes.data_fw_obj[pipe]); in mes_v11_0_allocate_ucode_data_buffer()
849 amdgpu_bo_free_kernel(&adev->mes.data_fw_obj[pipe], in mes_v11_0_free_ucode_buffers()
850 &adev->mes.data_fw_gpu_addr[pipe], in mes_v11_0_free_ucode_buffers()
851 (void **)&adev->mes.data_fw_ptr[pipe]); in mes_v11_0_free_ucode_buffers()
853 amdgpu_bo_free_kernel(&adev->mes.ucode_fw_obj[pipe], in mes_v11_0_free_ucode_buffers()
854 &adev->mes.ucode_fw_gpu_addr[pipe], in mes_v11_0_free_ucode_buffers()
855 (void **)&adev->mes.ucode_fw_ptr[pipe]); in mes_v11_0_free_ucode_buffers()
869 adev->mes.sched_version = in mes_v11_0_get_fw_version()
872 adev->mes.kiq_version = in mes_v11_0_get_fw_version()
900 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; in mes_v11_0_enable()
943 if (!adev->mes.fw[pipe]) in mes_v11_0_load_microcode()
963 ucode_addr = adev->mes.uc_start_addr[pipe] >> 2; in mes_v11_0_load_microcode()
971 lower_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v11_0_load_microcode()
973 upper_32_bits(adev->mes.ucode_fw_gpu_addr[pipe])); in mes_v11_0_load_microcode()
980 lower_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v11_0_load_microcode()
982 upper_32_bits(adev->mes.data_fw_gpu_addr[pipe])); in mes_v11_0_load_microcode()
1014 &adev->mes.eop_gpu_obj[pipe], in mes_v11_0_allocate_eop_buf()
1015 &adev->mes.eop_gpu_addr[pipe], in mes_v11_0_allocate_eop_buf()
1023 adev->mes.eop_gpu_obj[pipe]->tbo.base.size); in mes_v11_0_allocate_eop_buf()
1025 amdgpu_bo_kunmap(adev->mes.eop_gpu_obj[pipe]); in mes_v11_0_allocate_eop_buf()
1026 amdgpu_bo_unreserve(adev->mes.eop_gpu_obj[pipe]); in mes_v11_0_allocate_eop_buf()
1212 kiq->pmf->kiq_map_queues(kiq_ring, &adev->mes.ring[0]); in mes_v11_0_kiq_enable_queue()
1226 ring = &adev->mes.ring[0]; in mes_v11_0_queue_init()
1256 ring = &adev->mes.ring[0]; in mes_v11_0_ring_init()
1267 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_SCHED_PIPE]; in mes_v11_0_ring_init()
1291 ring->eop_gpu_addr = adev->mes.eop_gpu_addr[AMDGPU_MES_KIQ_PIPE]; in mes_v11_0_kiq_ring_init()
1309 ring = &adev->mes.ring[0]; in mes_v11_0_mqd_sw_init()
1328 adev->mes.mqd_backup[pipe] = kmalloc(mqd_size, GFP_KERNEL); in mes_v11_0_mqd_sw_init()
1329 if (!adev->mes.mqd_backup[pipe]) { in mes_v11_0_mqd_sw_init()
1344 adev->mes.funcs = &mes_v11_0_funcs; in mes_v11_0_sw_init()
1345 adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init; in mes_v11_0_sw_init()
1346 adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini; in mes_v11_0_sw_init()
1348 adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; in mes_v11_0_sw_init()
1386 kfree(adev->mes.mqd_backup[pipe]); in mes_v11_0_sw_fini()
1388 amdgpu_bo_free_kernel(&adev->mes.eop_gpu_obj[pipe], in mes_v11_0_sw_fini()
1389 &adev->mes.eop_gpu_addr[pipe], in mes_v11_0_sw_fini()
1391 amdgpu_ucode_release(&adev->mes.fw[pipe]); in mes_v11_0_sw_fini()
1398 amdgpu_bo_free_kernel(&adev->mes.ring[0].mqd_obj, in mes_v11_0_sw_fini()
1399 &adev->mes.ring[0].mqd_gpu_addr, in mes_v11_0_sw_fini()
1400 &adev->mes.ring[0].mqd_ptr); in mes_v11_0_sw_fini()
1403 amdgpu_ring_fini(&adev->mes.ring[0]); in mes_v11_0_sw_fini()
1503 if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) in mes_v11_0_kiq_hw_init()
1504 adev->mes.enable_legacy_queue_map = true; in mes_v11_0_kiq_hw_init()
1506 adev->mes.enable_legacy_queue_map = false; in mes_v11_0_kiq_hw_init()
1508 if (adev->mes.enable_legacy_queue_map) { in mes_v11_0_kiq_hw_init()
1523 if (adev->mes.ring[0].sched.ready) { in mes_v11_0_kiq_hw_fini()
1524 mes_v11_0_kiq_dequeue(&adev->mes.ring[0]); in mes_v11_0_kiq_hw_fini()
1525 adev->mes.ring[0].sched.ready = false; in mes_v11_0_kiq_hw_fini()
1543 if (adev->mes.ring[0].sched.ready) in mes_v11_0_hw_init()
1563 r = mes_v11_0_set_hw_resources(&adev->mes); in mes_v11_0_hw_init()
1568 r = mes_v11_0_set_hw_resources_1(&adev->mes); in mes_v11_0_hw_init()
1575 r = mes_v11_0_query_sched_status(&adev->mes); in mes_v11_0_hw_init()
1588 adev->mes.ring[0].sched.ready = true; in mes_v11_0_hw_init()
1601 amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, in mes_v11_0_hw_fini()
1602 &adev->mes.resource_1_addr); in mes_v11_0_hw_fini()