Lines Matching refs:mqd
1033 struct v11_compute_mqd *mqd = ring->mqd_ptr; in mes_v11_0_mqd_init() local
1037 memset(mqd, 0, sizeof(*mqd)); in mes_v11_0_mqd_init()
1039 mqd->header = 0xC0310800; in mes_v11_0_mqd_init()
1040 mqd->compute_pipelinestat_enable = 0x00000001; in mes_v11_0_mqd_init()
1041 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; in mes_v11_0_mqd_init()
1042 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; in mes_v11_0_mqd_init()
1043 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; in mes_v11_0_mqd_init()
1044 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; in mes_v11_0_mqd_init()
1045 mqd->compute_misc_reserved = 0x00000007; in mes_v11_0_mqd_init()
1054 mqd->cp_hqd_eop_base_addr_lo = lower_32_bits(eop_base_addr); in mes_v11_0_mqd_init()
1055 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); in mes_v11_0_mqd_init()
1056 mqd->cp_hqd_eop_control = tmp; in mes_v11_0_mqd_init()
1060 mqd->cp_hqd_pq_rptr = 0; in mes_v11_0_mqd_init()
1061 mqd->cp_hqd_pq_wptr_lo = 0; in mes_v11_0_mqd_init()
1062 mqd->cp_hqd_pq_wptr_hi = 0; in mes_v11_0_mqd_init()
1065 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; in mes_v11_0_mqd_init()
1066 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); in mes_v11_0_mqd_init()
1071 mqd->cp_mqd_control = tmp; in mes_v11_0_mqd_init()
1075 mqd->cp_hqd_pq_base_lo = lower_32_bits(hqd_gpu_addr); in mes_v11_0_mqd_init()
1076 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); in mes_v11_0_mqd_init()
1080 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; in mes_v11_0_mqd_init()
1081 mqd->cp_hqd_pq_rptr_report_addr_hi = in mes_v11_0_mqd_init()
1086 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffff8; in mes_v11_0_mqd_init()
1087 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; in mes_v11_0_mqd_init()
1100 mqd->cp_hqd_pq_control = tmp; in mes_v11_0_mqd_init()
1116 mqd->cp_hqd_pq_doorbell_control = tmp; in mes_v11_0_mqd_init()
1118 mqd->cp_hqd_vmid = 0; in mes_v11_0_mqd_init()
1120 mqd->cp_hqd_active = 1; in mes_v11_0_mqd_init()
1125 mqd->cp_hqd_persistent_state = tmp; in mes_v11_0_mqd_init()
1127 mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; in mes_v11_0_mqd_init()
1128 mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; in mes_v11_0_mqd_init()
1129 mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; in mes_v11_0_mqd_init()
1137 struct v11_compute_mqd *mqd = ring->mqd_ptr; in mes_v11_0_queue_init_register() local
1156 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); in mes_v11_0_queue_init_register()
1157 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in mes_v11_0_queue_init_register()
1165 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v11_0_queue_init_register()
1166 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v11_0_queue_init_register()
1170 mqd->cp_hqd_pq_rptr_report_addr_lo); in mes_v11_0_queue_init_register()
1172 mqd->cp_hqd_pq_rptr_report_addr_hi); in mes_v11_0_queue_init_register()
1175 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
1179 mqd->cp_hqd_pq_wptr_poll_addr_lo); in mes_v11_0_queue_init_register()
1181 mqd->cp_hqd_pq_wptr_poll_addr_hi); in mes_v11_0_queue_init_register()
1185 mqd->cp_hqd_pq_doorbell_control); in mes_v11_0_queue_init_register()
1188 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); in mes_v11_0_queue_init_register()
1191 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v11_0_queue_init_register()