Lines Matching refs:adev
37 static void xgpu_ai_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_ai_mailbox_send_ack() argument
42 static void xgpu_ai_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_ai_mailbox_set_valid() argument
56 static enum idh_event xgpu_ai_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_ai_mailbox_peek_msg() argument
63 static int xgpu_ai_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_ai_mailbox_rcv_msg() argument
73 xgpu_ai_mailbox_send_ack(adev); in xgpu_ai_mailbox_rcv_msg()
78 static uint8_t xgpu_ai_peek_ack(struct amdgpu_device *adev) { in xgpu_ai_peek_ack() argument
82 static int xgpu_ai_poll_ack(struct amdgpu_device *adev) in xgpu_ai_poll_ack() argument
96 dev_err(adev->dev, "Doesn't get TRN_MSG_ACK from pf in %d msec\n", AI_MAILBOX_POLL_ACK_TIMEDOUT); in xgpu_ai_poll_ack()
101 static int xgpu_ai_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_ai_poll_msg() argument
106 r = xgpu_ai_mailbox_rcv_msg(adev, event); in xgpu_ai_poll_msg()
114 dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r); in xgpu_ai_poll_msg()
119 static void xgpu_ai_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_ai_mailbox_trans_msg() argument
132 xgpu_ai_mailbox_set_valid(adev, false); in xgpu_ai_mailbox_trans_msg()
133 trn = xgpu_ai_peek_ack(adev); in xgpu_ai_mailbox_trans_msg()
135 dev_err_ratelimited(adev->dev, "trn=%x ACK should not assert! wait again !\n", trn); in xgpu_ai_mailbox_trans_msg()
153 xgpu_ai_mailbox_set_valid(adev, true); in xgpu_ai_mailbox_trans_msg()
156 r = xgpu_ai_poll_ack(adev); in xgpu_ai_mailbox_trans_msg()
158 dev_err(adev->dev, "Doesn't get ack from pf, continue\n"); in xgpu_ai_mailbox_trans_msg()
160 xgpu_ai_mailbox_set_valid(adev, false); in xgpu_ai_mailbox_trans_msg()
163 static int xgpu_ai_send_access_requests(struct amdgpu_device *adev, in xgpu_ai_send_access_requests() argument
168 xgpu_ai_mailbox_trans_msg(adev, req, 0, 0, 0); in xgpu_ai_send_access_requests()
174 r = xgpu_ai_poll_msg(adev, IDH_READY_TO_ACCESS_GPU); in xgpu_ai_send_access_requests()
176 dev_err(adev->dev, "Doesn't get READY_TO_ACCESS_GPU from pf, give up\n"); in xgpu_ai_send_access_requests()
181 adev->virt.fw_reserve.checksum_key = in xgpu_ai_send_access_requests()
187 r = xgpu_ai_poll_msg(adev, IDH_REQ_GPU_INIT_DATA_READY); in xgpu_ai_send_access_requests()
189 adev->virt.req_init_data_ver = 0; in xgpu_ai_send_access_requests()
195 static int xgpu_ai_request_reset(struct amdgpu_device *adev) in xgpu_ai_request_reset() argument
200 ret = xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); in xgpu_ai_request_reset()
209 static int xgpu_ai_request_full_gpu_access(struct amdgpu_device *adev, in xgpu_ai_request_full_gpu_access() argument
215 return xgpu_ai_send_access_requests(adev, req); in xgpu_ai_request_full_gpu_access()
218 static int xgpu_ai_release_full_gpu_access(struct amdgpu_device *adev, in xgpu_ai_release_full_gpu_access() argument
225 r = xgpu_ai_send_access_requests(adev, req); in xgpu_ai_release_full_gpu_access()
230 static int xgpu_ai_mailbox_ack_irq(struct amdgpu_device *adev, in xgpu_ai_mailbox_ack_irq() argument
234 dev_dbg(adev->dev, "get ack intr and do nothing.\n"); in xgpu_ai_mailbox_ack_irq()
238 static int xgpu_ai_set_mailbox_ack_irq(struct amdgpu_device *adev, in xgpu_ai_set_mailbox_ack_irq() argument
252 static void xgpu_ai_ready_to_reset(struct amdgpu_device *adev) in xgpu_ai_ready_to_reset() argument
254 xgpu_ai_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0); in xgpu_ai_ready_to_reset()
257 static int xgpu_ai_wait_reset(struct amdgpu_device *adev) in xgpu_ai_wait_reset() argument
261 if (xgpu_ai_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) { in xgpu_ai_wait_reset()
262 …dev_dbg(adev->dev, "Got AI IDH_FLR_NOTIFICATION_CMPL after %d ms\n", AI_MAILBOX_POLL_FLR_TIMEDOUT … in xgpu_ai_wait_reset()
269 dev_dbg(adev->dev, "waiting AI IDH_FLR_NOTIFICATION_CMPL timeout\n"); in xgpu_ai_wait_reset()
276 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_ai_mailbox_flr_work() local
278 amdgpu_virt_fini_data_exchange(adev); in xgpu_ai_mailbox_flr_work()
281 if (amdgpu_device_should_recover_gpu(adev) in xgpu_ai_mailbox_flr_work()
282 && (!amdgpu_device_has_job_running(adev) || in xgpu_ai_mailbox_flr_work()
283 adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT)) { in xgpu_ai_mailbox_flr_work()
288 reset_context.reset_req_dev = adev; in xgpu_ai_mailbox_flr_work()
292 amdgpu_device_gpu_recover(adev, NULL, &reset_context); in xgpu_ai_mailbox_flr_work()
296 static int xgpu_ai_set_mailbox_rcv_irq(struct amdgpu_device *adev, in xgpu_ai_set_mailbox_rcv_irq() argument
310 static int xgpu_ai_mailbox_rcv_irq(struct amdgpu_device *adev, in xgpu_ai_mailbox_rcv_irq() argument
314 enum idh_event event = xgpu_ai_mailbox_peek_msg(adev); in xgpu_ai_mailbox_rcv_irq()
318 if (amdgpu_sriov_runtime(adev)) in xgpu_ai_mailbox_rcv_irq()
319 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain, in xgpu_ai_mailbox_rcv_irq()
320 &adev->virt.flr_work), in xgpu_ai_mailbox_rcv_irq()
325 xgpu_ai_mailbox_send_ack(adev); in xgpu_ai_mailbox_rcv_irq()
351 void xgpu_ai_mailbox_set_irq_funcs(struct amdgpu_device *adev) in xgpu_ai_mailbox_set_irq_funcs() argument
353 adev->virt.ack_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
354 adev->virt.ack_irq.funcs = &xgpu_ai_mailbox_ack_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
355 adev->virt.rcv_irq.num_types = 1; in xgpu_ai_mailbox_set_irq_funcs()
356 adev->virt.rcv_irq.funcs = &xgpu_ai_mailbox_rcv_irq_funcs; in xgpu_ai_mailbox_set_irq_funcs()
359 int xgpu_ai_mailbox_add_irq_id(struct amdgpu_device *adev) in xgpu_ai_mailbox_add_irq_id() argument
363 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_ai_mailbox_add_irq_id()
367 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
369 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_add_irq_id()
376 int xgpu_ai_mailbox_get_irq(struct amdgpu_device *adev) in xgpu_ai_mailbox_get_irq() argument
380 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
383 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
385 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
389 INIT_WORK(&adev->virt.flr_work, xgpu_ai_mailbox_flr_work); in xgpu_ai_mailbox_get_irq()
394 void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev) in xgpu_ai_mailbox_put_irq() argument
396 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
397 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_put_irq()
400 static int xgpu_ai_request_init_data(struct amdgpu_device *adev) in xgpu_ai_request_init_data() argument
402 return xgpu_ai_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA); in xgpu_ai_request_init_data()
405 static void xgpu_ai_ras_poison_handler(struct amdgpu_device *adev, in xgpu_ai_ras_poison_handler() argument
408 xgpu_ai_send_access_requests(adev, IDH_RAS_POISON); in xgpu_ai_ras_poison_handler()
411 static bool xgpu_ai_rcvd_ras_intr(struct amdgpu_device *adev) in xgpu_ai_rcvd_ras_intr() argument
413 enum idh_event msg = xgpu_ai_mailbox_peek_msg(adev); in xgpu_ai_rcvd_ras_intr()