Lines Matching refs:adev
36 static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev) in xgpu_nv_mailbox_send_ack() argument
41 static void xgpu_nv_mailbox_set_valid(struct amdgpu_device *adev, bool val) in xgpu_nv_mailbox_set_valid() argument
55 static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev) in xgpu_nv_mailbox_peek_msg() argument
61 static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev, in xgpu_nv_mailbox_rcv_msg() argument
70 xgpu_nv_mailbox_send_ack(adev); in xgpu_nv_mailbox_rcv_msg()
75 static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev) in xgpu_nv_peek_ack() argument
80 static int xgpu_nv_poll_ack(struct amdgpu_device *adev) in xgpu_nv_poll_ack() argument
94 dev_err(adev->dev, "Doesn't get TRN_MSG_ACK from pf in %d msec \n", NV_MAILBOX_POLL_ACK_TIMEDOUT); in xgpu_nv_poll_ack()
99 static int xgpu_nv_poll_msg(struct amdgpu_device *adev, enum idh_event event) in xgpu_nv_poll_msg() argument
108 r = xgpu_nv_mailbox_rcv_msg(adev, event); in xgpu_nv_poll_msg()
110 …dev_dbg(adev->dev, "rcv_msg 0x%x after %llu ms\n", event, NV_MAILBOX_POLL_MSG_TIMEDOUT - timeout +… in xgpu_nv_poll_msg()
118 dev_dbg(adev->dev, "nv_poll_msg timed out\n"); in xgpu_nv_poll_msg()
123 static void xgpu_nv_mailbox_trans_msg (struct amdgpu_device *adev, in xgpu_nv_mailbox_trans_msg() argument
136 xgpu_nv_mailbox_set_valid(adev, false); in xgpu_nv_mailbox_trans_msg()
137 trn = xgpu_nv_peek_ack(adev); in xgpu_nv_mailbox_trans_msg()
139 dev_err_ratelimited(adev->dev, "trn=%x ACK should not assert! wait again !\n", trn); in xgpu_nv_mailbox_trans_msg()
144 dev_dbg(adev->dev, "trans_msg req = 0x%x, data1 = 0x%x\n", req, data1); in xgpu_nv_mailbox_trans_msg()
149 xgpu_nv_mailbox_set_valid(adev, true); in xgpu_nv_mailbox_trans_msg()
152 r = xgpu_nv_poll_ack(adev); in xgpu_nv_mailbox_trans_msg()
154 dev_err(adev->dev, "Doesn't get ack from pf, continue\n"); in xgpu_nv_mailbox_trans_msg()
156 xgpu_nv_mailbox_set_valid(adev, false); in xgpu_nv_mailbox_trans_msg()
159 static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, in xgpu_nv_send_access_requests_with_param() argument
166 xgpu_nv_mailbox_trans_msg(adev, req, data1, data2, data3); in xgpu_nv_send_access_requests_with_param()
186 r = xgpu_nv_poll_msg(adev, event); in xgpu_nv_send_access_requests_with_param()
192 dev_err(adev->dev, "Doesn't get msg:%d from pf, error=%d\n", event, r); in xgpu_nv_send_access_requests_with_param()
195 adev->virt.req_init_data_ver = 0; in xgpu_nv_send_access_requests_with_param()
198 adev->virt.req_init_data_ver = in xgpu_nv_send_access_requests_with_param()
202 if (adev->virt.req_init_data_ver < 1) in xgpu_nv_send_access_requests_with_param()
203 adev->virt.req_init_data_ver = 1; in xgpu_nv_send_access_requests_with_param()
209 adev->virt.fw_reserve.checksum_key = in xgpu_nv_send_access_requests_with_param()
217 static int xgpu_nv_send_access_requests(struct amdgpu_device *adev, in xgpu_nv_send_access_requests() argument
220 return xgpu_nv_send_access_requests_with_param(adev, in xgpu_nv_send_access_requests()
224 static int xgpu_nv_request_reset(struct amdgpu_device *adev) in xgpu_nv_request_reset() argument
229 ret = xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_RESET_ACCESS); in xgpu_nv_request_reset()
238 static int xgpu_nv_request_full_gpu_access(struct amdgpu_device *adev, in xgpu_nv_request_full_gpu_access() argument
244 return xgpu_nv_send_access_requests(adev, req); in xgpu_nv_request_full_gpu_access()
247 static int xgpu_nv_release_full_gpu_access(struct amdgpu_device *adev, in xgpu_nv_release_full_gpu_access() argument
254 r = xgpu_nv_send_access_requests(adev, req); in xgpu_nv_release_full_gpu_access()
259 static int xgpu_nv_request_init_data(struct amdgpu_device *adev) in xgpu_nv_request_init_data() argument
261 return xgpu_nv_send_access_requests(adev, IDH_REQ_GPU_INIT_DATA); in xgpu_nv_request_init_data()
264 static int xgpu_nv_mailbox_ack_irq(struct amdgpu_device *adev, in xgpu_nv_mailbox_ack_irq() argument
268 dev_dbg(adev->dev, "get ack intr and do nothing.\n"); in xgpu_nv_mailbox_ack_irq()
272 static int xgpu_nv_set_mailbox_ack_irq(struct amdgpu_device *adev, in xgpu_nv_set_mailbox_ack_irq() argument
289 static void xgpu_nv_ready_to_reset(struct amdgpu_device *adev) in xgpu_nv_ready_to_reset() argument
291 xgpu_nv_mailbox_trans_msg(adev, IDH_READY_TO_RESET, 0, 0, 0); in xgpu_nv_ready_to_reset()
294 static int xgpu_nv_wait_reset(struct amdgpu_device *adev) in xgpu_nv_wait_reset() argument
298 if (xgpu_nv_mailbox_peek_msg(adev) == IDH_FLR_NOTIFICATION_CMPL) { in xgpu_nv_wait_reset()
299 …dev_dbg(adev->dev, "Got NV IDH_FLR_NOTIFICATION_CMPL after %d ms\n", NV_MAILBOX_POLL_FLR_TIMEDOUT … in xgpu_nv_wait_reset()
306 dev_dbg(adev->dev, "waiting NV IDH_FLR_NOTIFICATION_CMPL timeout\n"); in xgpu_nv_wait_reset()
313 struct amdgpu_device *adev = container_of(virt, struct amdgpu_device, virt); in xgpu_nv_mailbox_flr_work() local
315 amdgpu_virt_fini_data_exchange(adev); in xgpu_nv_mailbox_flr_work()
318 if (amdgpu_device_should_recover_gpu(adev) in xgpu_nv_mailbox_flr_work()
319 && (!amdgpu_device_has_job_running(adev) || in xgpu_nv_mailbox_flr_work()
320 adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT || in xgpu_nv_mailbox_flr_work()
321 adev->gfx_timeout == MAX_SCHEDULE_TIMEOUT || in xgpu_nv_mailbox_flr_work()
322 adev->compute_timeout == MAX_SCHEDULE_TIMEOUT || in xgpu_nv_mailbox_flr_work()
323 adev->video_timeout == MAX_SCHEDULE_TIMEOUT)) { in xgpu_nv_mailbox_flr_work()
328 reset_context.reset_req_dev = adev; in xgpu_nv_mailbox_flr_work()
332 amdgpu_device_gpu_recover(adev, NULL, &reset_context); in xgpu_nv_mailbox_flr_work()
336 static int xgpu_nv_set_mailbox_rcv_irq(struct amdgpu_device *adev, in xgpu_nv_set_mailbox_rcv_irq() argument
353 static int xgpu_nv_mailbox_rcv_irq(struct amdgpu_device *adev, in xgpu_nv_mailbox_rcv_irq() argument
357 enum idh_event event = xgpu_nv_mailbox_peek_msg(adev); in xgpu_nv_mailbox_rcv_irq()
361 if (amdgpu_sriov_runtime(adev)) in xgpu_nv_mailbox_rcv_irq()
362 WARN_ONCE(!amdgpu_reset_domain_schedule(adev->reset_domain, in xgpu_nv_mailbox_rcv_irq()
363 &adev->virt.flr_work), in xgpu_nv_mailbox_rcv_irq()
391 void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev) in xgpu_nv_mailbox_set_irq_funcs() argument
393 adev->virt.ack_irq.num_types = 1; in xgpu_nv_mailbox_set_irq_funcs()
394 adev->virt.ack_irq.funcs = &xgpu_nv_mailbox_ack_irq_funcs; in xgpu_nv_mailbox_set_irq_funcs()
395 adev->virt.rcv_irq.num_types = 1; in xgpu_nv_mailbox_set_irq_funcs()
396 adev->virt.rcv_irq.funcs = &xgpu_nv_mailbox_rcv_irq_funcs; in xgpu_nv_mailbox_set_irq_funcs()
399 int xgpu_nv_mailbox_add_irq_id(struct amdgpu_device *adev) in xgpu_nv_mailbox_add_irq_id() argument
403 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_nv_mailbox_add_irq_id()
407 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_nv_mailbox_add_irq_id()
409 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_add_irq_id()
416 int xgpu_nv_mailbox_get_irq(struct amdgpu_device *adev) in xgpu_nv_mailbox_get_irq() argument
420 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
423 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_get_irq()
425 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_get_irq()
429 INIT_WORK(&adev->virt.flr_work, xgpu_nv_mailbox_flr_work); in xgpu_nv_mailbox_get_irq()
434 void xgpu_nv_mailbox_put_irq(struct amdgpu_device *adev) in xgpu_nv_mailbox_put_irq() argument
436 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_nv_mailbox_put_irq()
437 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_nv_mailbox_put_irq()
440 static void xgpu_nv_ras_poison_handler(struct amdgpu_device *adev, in xgpu_nv_ras_poison_handler() argument
443 if (amdgpu_ip_version(adev, UMC_HWIP, 0) < IP_VERSION(12, 0, 0)) { in xgpu_nv_ras_poison_handler()
444 xgpu_nv_send_access_requests(adev, IDH_RAS_POISON); in xgpu_nv_ras_poison_handler()
446 amdgpu_virt_fini_data_exchange(adev); in xgpu_nv_ras_poison_handler()
447 xgpu_nv_send_access_requests_with_param(adev, in xgpu_nv_ras_poison_handler()
452 static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev) in xgpu_nv_rcvd_ras_intr() argument
454 enum idh_event msg = xgpu_nv_mailbox_peek_msg(adev); in xgpu_nv_rcvd_ras_intr()