Lines Matching refs:adev
174 static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode, in soc15_query_video_codecs() argument
177 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
178 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { in soc15_query_video_codecs()
190 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { in soc15_query_video_codecs()
218 static u32 soc15_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) in soc15_uvd_ctx_rreg() argument
226 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
229 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
233 static void soc15_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_uvd_ctx_wreg() argument
240 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
243 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
246 static u32 soc15_didt_rreg(struct amdgpu_device *adev, u32 reg) in soc15_didt_rreg() argument
254 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
257 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
261 static void soc15_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_didt_wreg() argument
268 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
271 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
274 static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_gc_cac_rreg() argument
279 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
282 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
286 static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_gc_cac_wreg() argument
290 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
293 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
296 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) in soc15_se_cac_rreg() argument
301 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
304 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
308 static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v) in soc15_se_cac_wreg() argument
312 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
315 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
318 static u32 soc15_get_config_memsize(struct amdgpu_device *adev) in soc15_get_config_memsize() argument
320 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
323 static u32 soc15_get_xclk(struct amdgpu_device *adev) in soc15_get_xclk() argument
325 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
327 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
328 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
329 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || in soc15_get_xclk()
330 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) in soc15_get_xclk()
332 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
333 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
340 void soc15_grbm_select(struct amdgpu_device *adev, in soc15_grbm_select() argument
352 static bool soc15_read_disabled_bios(struct amdgpu_device *adev) in soc15_read_disabled_bios() argument
381 static uint32_t soc15_read_indexed_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_indexed_register() argument
386 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
388 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0); in soc15_read_indexed_register()
393 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0); in soc15_read_indexed_register()
394 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
398 static uint32_t soc15_get_register_value(struct amdgpu_device *adev, in soc15_get_register_value() argument
403 return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset); in soc15_get_register_value()
406 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
408 return adev->gfx.config.db_debug2; in soc15_get_register_value()
413 static int soc15_read_register(struct amdgpu_device *adev, u32 se_num, in soc15_read_register() argument
422 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
424 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
428 *value = soc15_get_register_value(adev, in soc15_read_register()
448 void soc15_program_register_sequence(struct amdgpu_device *adev, in soc15_program_register_sequence() argument
458 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
483 static int soc15_asic_baco_reset(struct amdgpu_device *adev) in soc15_asic_baco_reset() argument
485 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset()
489 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
490 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
492 ret = amdgpu_dpm_baco_reset(adev); in soc15_asic_baco_reset()
497 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
498 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
504 soc15_asic_reset_method(struct amdgpu_device *adev) in soc15_asic_reset_method() argument
508 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method()
510 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) in soc15_asic_reset_method()
524 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
527 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_asic_reset_method()
535 if (adev->asic_type == CHIP_VEGA20) { in soc15_asic_reset_method()
536 if (adev->psp.sos.fw_version >= 0x80067) in soc15_asic_reset_method()
537 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
542 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
543 adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
546 baco_reset = amdgpu_dpm_is_baco_supported(adev); in soc15_asic_reset_method()
565 else if (!(adev->flags & AMD_IS_APU)) in soc15_asic_reset_method()
579 static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) in soc15_need_reset_on_resume() argument
589 if (adev->flags & AMD_IS_APU && adev->in_s3 && in soc15_need_reset_on_resume()
590 !adev->suspend_complete && in soc15_need_reset_on_resume()
597 static int soc15_asic_reset(struct amdgpu_device *adev) in soc15_asic_reset() argument
604 if (((adev->apu_flags & AMD_APU_IS_RAVEN) || in soc15_asic_reset()
605 (adev->apu_flags & AMD_APU_IS_RAVEN2)) && in soc15_asic_reset()
606 !soc15_need_reset_on_resume(adev)) in soc15_asic_reset()
609 switch (soc15_asic_reset_method(adev)) { in soc15_asic_reset()
611 dev_info(adev->dev, "PCI reset\n"); in soc15_asic_reset()
612 return amdgpu_device_pci_reset(adev); in soc15_asic_reset()
614 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
615 return soc15_asic_baco_reset(adev); in soc15_asic_reset()
617 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
618 return amdgpu_dpm_mode2_reset(adev); in soc15_asic_reset()
620 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
621 return amdgpu_device_mode1_reset(adev); in soc15_asic_reset()
625 static int soc15_supports_baco(struct amdgpu_device *adev) in soc15_supports_baco() argument
627 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_supports_baco()
630 if (adev->asic_type == CHIP_VEGA20) { in soc15_supports_baco()
631 if (adev->psp.sos.fw_version >= 0x80067) in soc15_supports_baco()
632 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
635 return amdgpu_dpm_is_baco_supported(adev); in soc15_supports_baco()
649 static int soc15_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) in soc15_set_uvd_clocks() argument
662 static int soc15_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) in soc15_set_vce_clocks() argument
669 static void soc15_program_aspm(struct amdgpu_device *adev) in soc15_program_aspm() argument
671 if (!amdgpu_device_should_use_aspm(adev)) in soc15_program_aspm()
674 if (adev->nbio.funcs->program_aspm) in soc15_program_aspm()
675 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
687 static void soc15_reg_base_init(struct amdgpu_device *adev) in soc15_reg_base_init() argument
690 switch (adev->asic_type) { in soc15_reg_base_init()
695 vega10_reg_base_init(adev); in soc15_reg_base_init()
698 vega20_reg_base_init(adev); in soc15_reg_base_init()
701 arct_reg_base_init(adev); in soc15_reg_base_init()
704 aldebaran_reg_base_init(adev); in soc15_reg_base_init()
707 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
712 void soc15_set_virt_ops(struct amdgpu_device *adev) in soc15_set_virt_ops() argument
714 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
719 soc15_reg_base_init(adev); in soc15_set_virt_ops()
722 static bool soc15_need_full_reset(struct amdgpu_device *adev) in soc15_need_full_reset() argument
728 static void soc15_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in soc15_get_pcie_usage() argument
738 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
775 static void vega20_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, in vega20_get_pcie_usage() argument
785 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
824 static bool soc15_need_reset_on_init(struct amdgpu_device *adev) in soc15_need_reset_on_init() argument
829 if (adev->asic_type == CHIP_RENOIR) in soc15_need_reset_on_init()
835 if (!amdgpu_passthrough(adev)) in soc15_need_reset_on_init()
838 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
851 static uint64_t soc15_get_pcie_replay_count(struct amdgpu_device *adev) in soc15_get_pcie_replay_count() argument
863 static void soc15_pre_asic_init(struct amdgpu_device *adev) in soc15_pre_asic_init() argument
865 gmc_v9_0_restore_registers(adev); in soc15_pre_asic_init()
934 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_early_init() local
936 adev->nbio.funcs->set_reg_remap(adev); in soc15_common_early_init()
937 adev->smc_rreg = NULL; in soc15_common_early_init()
938 adev->smc_wreg = NULL; in soc15_common_early_init()
939 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc15_common_early_init()
940 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc15_common_early_init()
941 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; in soc15_common_early_init()
942 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; in soc15_common_early_init()
943 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc15_common_early_init()
944 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc15_common_early_init()
945 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; in soc15_common_early_init()
946 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; in soc15_common_early_init()
947 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
948 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
949 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
950 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
951 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
952 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
953 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
954 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
956 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc15_common_early_init()
957 adev->external_rev_id = 0xFF; in soc15_common_early_init()
961 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { in soc15_common_early_init()
963 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
964 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
983 adev->pg_flags = 0; in soc15_common_early_init()
984 adev->external_rev_id = 0x1; in soc15_common_early_init()
987 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
988 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1006 adev->pg_flags = 0; in soc15_common_early_init()
1007 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1010 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1011 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1029 adev->pg_flags = 0; in soc15_common_early_init()
1030 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1034 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1036 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1037 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1039 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1040 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1041 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1042 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1043 else if (adev->rev_id == 1) in soc15_common_early_init()
1044 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1046 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1048 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1049 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1064 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1065 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1066 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1084 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1087 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1106 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1110 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1111 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1125 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1126 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1129 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1131 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1132 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1134 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1135 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1154 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1160 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1161 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1169 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1170 adev->external_rev_id = adev->rev_id + 0x3c; in soc15_common_early_init()
1174 adev->asic_funcs = &aqua_vanjaram_asic_funcs; in soc15_common_early_init()
1175 adev->cg_flags = in soc15_common_early_init()
1181 adev->pg_flags = in soc15_common_early_init()
1186 adev->external_rev_id = adev->rev_id + 0x46; in soc15_common_early_init()
1193 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1194 amdgpu_virt_init_setting(adev); in soc15_common_early_init()
1195 xgpu_ai_mailbox_set_irq_funcs(adev); in soc15_common_early_init()
1203 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_late_init() local
1205 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1206 xgpu_ai_mailbox_get_irq(adev); in soc15_common_late_init()
1211 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc15_common_late_init()
1218 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_init() local
1220 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1221 xgpu_ai_mailbox_add_irq_id(adev); in soc15_common_sw_init()
1223 if (adev->df.funcs && in soc15_common_sw_init()
1224 adev->df.funcs->sw_init) in soc15_common_sw_init()
1225 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1232 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_sw_fini() local
1234 if (adev->df.funcs && in soc15_common_sw_fini()
1235 adev->df.funcs->sw_fini) in soc15_common_sw_fini()
1236 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1240 static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) in soc15_sdma_doorbell_range_init() argument
1245 if (!amdgpu_sriov_vf(adev)) { in soc15_sdma_doorbell_range_init()
1246 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_sdma_doorbell_range_init()
1247 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1248 true, adev->doorbell_index.sdma_engine[i] << 1, in soc15_sdma_doorbell_range_init()
1249 adev->doorbell_index.sdma_doorbell_range); in soc15_sdma_doorbell_range_init()
1256 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_init() local
1259 soc15_program_aspm(adev); in soc15_common_hw_init()
1261 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1266 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1267 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1270 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1278 soc15_sdma_doorbell_range_init(adev); in soc15_common_hw_init()
1285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_hw_fini() local
1292 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1293 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc15_common_hw_fini()
1295 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1296 xgpu_ai_mailbox_put_irq(adev); in soc15_common_hw_fini()
1298 if ((!amdgpu_sriov_vf(adev)) && in soc15_common_hw_fini()
1299 adev->nbio.ras_if && in soc15_common_hw_fini()
1300 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1301 if (adev->nbio.ras && in soc15_common_hw_fini()
1302 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1303 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1304 if (adev->nbio.ras && in soc15_common_hw_fini()
1305 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1306 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_suspend() local
1316 return soc15_common_hw_fini(adev); in soc15_common_suspend()
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_resume() local
1323 if (soc15_need_reset_on_resume(adev)) { in soc15_common_resume()
1324 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); in soc15_common_resume()
1325 soc15_asic_reset(adev); in soc15_common_resume()
1327 return soc15_common_hw_init(adev); in soc15_common_resume()
1345 static void soc15_update_drm_clock_gating(struct amdgpu_device *adev, bool enable) in soc15_update_drm_clock_gating() argument
1351 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1374 static void soc15_update_drm_light_sleep(struct amdgpu_device *adev, bool enable) in soc15_update_drm_light_sleep() argument
1380 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1392 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_set_clockgating_state() local
1394 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1397 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc15_common_set_clockgating_state()
1401 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1403 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1405 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1407 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1409 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1411 adev->smuio.funcs->update_rom_clock_gating(adev, in soc15_common_set_clockgating_state()
1413 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1419 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1421 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1423 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1425 soc15_update_drm_clock_gating(adev, in soc15_common_set_clockgating_state()
1427 soc15_update_drm_light_sleep(adev, in soc15_common_set_clockgating_state()
1432 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1443 struct amdgpu_device *adev = (struct amdgpu_device *)handle; in soc15_common_get_clockgating_state() local
1446 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
1449 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1450 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1452 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1453 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1455 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && in soc15_common_get_clockgating_state()
1456 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && in soc15_common_get_clockgating_state()
1457 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { in soc15_common_get_clockgating_state()
1470 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1471 adev->smuio.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1473 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1474 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()