Lines Matching refs:handle
355 int (*pre_set_power_state)(void *handle);
356 int (*set_power_state)(void *handle);
357 void (*post_set_power_state)(void *handle);
358 void (*display_configuration_changed)(void *handle);
359 void (*print_power_state)(void *handle, void *ps);
360 bool (*vblank_too_short)(void *handle);
361 void (*enable_bapm)(void *handle, bool enable);
362 int (*check_state_equal)(void *handle,
367 int (*set_fan_control_mode)(void *handle, u32 mode);
368 int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
369 int (*set_fan_speed_pwm)(void *handle, u32 speed);
370 int (*get_fan_speed_pwm)(void *handle, u32 *speed);
371 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
372 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
373 int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
374 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
375 int (*get_sclk_od)(void *handle);
376 int (*set_sclk_od)(void *handle, uint32_t value);
377 int (*get_mclk_od)(void *handle);
378 int (*set_mclk_od)(void *handle, uint32_t value);
379 int (*read_sensor)(void *handle, int idx, void *value, int *size);
380 int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
381 int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
382 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
383 enum amd_pm_state_type (*get_current_power_state)(void *handle);
384 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
385 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
386 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
387 int (*get_pp_table)(void *handle, char **table);
388 int (*set_pp_table)(void *handle, const char *buf, size_t size);
389 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
390 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
392 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
393 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
395 int (*load_firmware)(void *handle);
396 int (*wait_for_fw_loading_complete)(void *handle);
397 int (*set_powergating_by_smu)(void *handle,
399 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
400 int (*set_power_limit)(void *handle, uint32_t n);
401 int (*get_power_limit)(void *handle, uint32_t *limit,
404 int (*get_power_profile_mode)(void *handle, char *buf);
405 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
406 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
407 int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
409 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
410 int (*smu_i2c_bus_access)(void *handle, bool acquire);
411 int (*gfx_state_change_set)(void *handle, uint32_t state);
413 u32 (*get_sclk)(void *handle, bool low);
414 u32 (*get_mclk)(void *handle, bool low);
415 int (*display_configuration_change)(void *handle,
417 int (*get_display_power_level)(void *handle,
419 int (*get_current_clocks)(void *handle,
421 int (*get_clock_by_type)(void *handle,
424 int (*get_clock_by_type_with_latency)(void *handle,
427 int (*get_clock_by_type_with_voltage)(void *handle,
430 int (*set_watermarks_for_clocks_ranges)(void *handle,
432 int (*display_clock_voltage_request)(void *handle,
434 int (*get_display_mode_validation_clocks)(void *handle,
436 int (*notify_smu_enable_pwe)(void *handle);
437 int (*enable_mgpu_fan_boost)(void *handle);
438 int (*set_active_display_count)(void *handle, uint32_t count);
439 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
440 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
441 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
442 int (*get_asic_baco_capability)(void *handle);
443 int (*get_asic_baco_state)(void *handle, int *state);
444 int (*set_asic_baco_state)(void *handle, int state);
445 int (*get_ppfeature_status)(void *handle, char *buf);
446 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
447 int (*asic_reset_mode_2)(void *handle);
448 int (*asic_reset_enable_gfx_features)(void *handle);
449 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
450 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
451 ssize_t (*get_gpu_metrics)(void *handle, void **table);
452 ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
453 int (*set_watermarks_for_clock_ranges)(void *handle,
455 int (*display_disable_memory_clock_switch)(void *handle,
457 int (*get_max_sustainable_clocks_by_dc)(void *handle,
459 int (*get_uclk_dpm_states)(void *handle,
462 int (*get_dpm_clock_table)(void *handle,
464 int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
465 void (*pm_compute_clocks)(void *handle);
466 int (*notify_rlc_state)(void *handle, bool en);