Lines Matching refs:adev
36 #define amdgpu_dpm_enable_bapm(adev, e) \ argument
37 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
39 #define amdgpu_dpm_is_legacy_dpm(adev) ((adev)->powerplay.pp_handle == (adev)) argument
41 int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_sclk() argument
43 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk()
49 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
50 ret = pp_funcs->get_sclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_sclk()
52 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk()
57 int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) in amdgpu_dpm_get_mclk() argument
59 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk()
65 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
66 ret = pp_funcs->get_mclk((adev)->powerplay.pp_handle, in amdgpu_dpm_get_mclk()
68 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk()
73 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) in amdgpu_dpm_set_powergating_by_smu() argument
76 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_powergating_by_smu()
79 if (atomic_read(&adev->pm.pwr_state[block_type]) == pwr_state) { in amdgpu_dpm_set_powergating_by_smu()
80 dev_dbg(adev->dev, "IP block%d already in the target %s state!", in amdgpu_dpm_set_powergating_by_smu()
85 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
99 (adev)->powerplay.pp_handle, block_type, gate)); in amdgpu_dpm_set_powergating_by_smu()
106 atomic_set(&adev->pm.pwr_state[block_type], pwr_state); in amdgpu_dpm_set_powergating_by_smu()
108 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_powergating_by_smu()
113 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev) in amdgpu_dpm_set_gfx_power_up_by_imu() argument
115 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_gfx_power_up_by_imu()
118 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
120 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_gfx_power_up_by_imu()
127 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev) in amdgpu_dpm_baco_enter() argument
129 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_enter()
130 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_enter()
136 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
141 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_enter()
146 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev) in amdgpu_dpm_baco_exit() argument
148 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_exit()
149 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_exit()
155 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
160 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_exit()
165 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, in amdgpu_dpm_set_mp1_state() argument
169 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mp1_state()
173 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_set_mp1_state()
174 adev->pm.dpm_enabled = false; in amdgpu_dpm_set_mp1_state()
176 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
179 adev->powerplay.pp_handle, in amdgpu_dpm_set_mp1_state()
182 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mp1_state()
188 int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en) in amdgpu_dpm_notify_rlc_state() argument
191 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_notify_rlc_state()
194 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_notify_rlc_state()
197 adev->powerplay.pp_handle, in amdgpu_dpm_notify_rlc_state()
200 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_notify_rlc_state()
206 int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_baco_supported() argument
208 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_is_baco_supported()
209 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_is_baco_supported()
223 if (adev->in_s3) in amdgpu_dpm_is_baco_supported()
226 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
230 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_baco_supported()
235 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode2_reset() argument
237 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_mode2_reset()
238 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_mode2_reset()
244 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
248 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode2_reset()
253 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev) in amdgpu_dpm_enable_gfx_features() argument
255 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_enable_gfx_features()
256 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_gfx_features()
262 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_gfx_features()
266 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_gfx_features()
271 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev) in amdgpu_dpm_baco_reset() argument
273 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_baco_reset()
274 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_baco_reset()
280 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
291 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_baco_reset()
295 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_mode1_reset_supported() argument
297 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_mode1_reset_supported()
300 if (is_support_sw_smu(adev)) { in amdgpu_dpm_is_mode1_reset_supported()
301 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
303 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_mode1_reset_supported()
309 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev) in amdgpu_dpm_mode1_reset() argument
311 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_mode1_reset()
314 if (is_support_sw_smu(adev)) { in amdgpu_dpm_mode1_reset()
315 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
317 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_mode1_reset()
323 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, in amdgpu_dpm_switch_power_profile() argument
327 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_switch_power_profile()
330 if (amdgpu_sriov_vf(adev)) in amdgpu_dpm_switch_power_profile()
334 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
336 adev->powerplay.pp_handle, type, en); in amdgpu_dpm_switch_power_profile()
337 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_switch_power_profile()
343 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, in amdgpu_dpm_set_xgmi_pstate() argument
346 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_xgmi_pstate()
350 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
351 ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle, in amdgpu_dpm_set_xgmi_pstate()
353 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_xgmi_pstate()
359 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, in amdgpu_dpm_set_df_cstate() argument
363 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_df_cstate()
364 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_df_cstate()
367 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
369 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_df_cstate()
375 ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, in amdgpu_dpm_get_pm_policy_info() argument
378 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_pm_policy_info()
381 if (is_support_sw_smu(adev)) { in amdgpu_dpm_get_pm_policy_info()
382 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pm_policy_info()
384 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pm_policy_info()
390 int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, in amdgpu_dpm_set_pm_policy() argument
393 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_pm_policy()
396 if (is_support_sw_smu(adev)) { in amdgpu_dpm_set_pm_policy()
397 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_pm_policy()
399 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_pm_policy()
405 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev) in amdgpu_dpm_enable_mgpu_fan_boost() argument
407 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_enable_mgpu_fan_boost()
409 adev->powerplay.pp_funcs; in amdgpu_dpm_enable_mgpu_fan_boost()
413 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
415 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_mgpu_fan_boost()
421 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, in amdgpu_dpm_set_clockgating_by_smu() argument
424 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_set_clockgating_by_smu()
426 adev->powerplay.pp_funcs; in amdgpu_dpm_set_clockgating_by_smu()
430 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
433 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_clockgating_by_smu()
439 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, in amdgpu_dpm_smu_i2c_bus_access() argument
442 void *pp_handle = adev->powerplay.pp_handle; in amdgpu_dpm_smu_i2c_bus_access()
444 adev->powerplay.pp_funcs; in amdgpu_dpm_smu_i2c_bus_access()
448 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
451 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_smu_i2c_bus_access()
457 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev) in amdgpu_pm_acpi_event_handler() argument
459 if (adev->pm.dpm_enabled) { in amdgpu_pm_acpi_event_handler()
460 mutex_lock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
462 adev->pm.ac_power = true; in amdgpu_pm_acpi_event_handler()
464 adev->pm.ac_power = false; in amdgpu_pm_acpi_event_handler()
466 if (adev->powerplay.pp_funcs && in amdgpu_pm_acpi_event_handler()
467 adev->powerplay.pp_funcs->enable_bapm) in amdgpu_pm_acpi_event_handler()
468 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
470 if (is_support_sw_smu(adev)) in amdgpu_pm_acpi_event_handler()
471 smu_set_ac_dc(adev->powerplay.pp_handle); in amdgpu_pm_acpi_event_handler()
473 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_acpi_event_handler()
477 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, in amdgpu_dpm_read_sensor() argument
480 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_read_sensor()
487 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
488 ret = pp_funcs->read_sensor(adev->powerplay.pp_handle, in amdgpu_dpm_read_sensor()
492 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_read_sensor()
498 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit) in amdgpu_dpm_get_apu_thermal_limit() argument
500 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_apu_thermal_limit()
504 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_apu_thermal_limit()
505 ret = pp_funcs->get_apu_thermal_limit(adev->powerplay.pp_handle, limit); in amdgpu_dpm_get_apu_thermal_limit()
506 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_apu_thermal_limit()
512 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit) in amdgpu_dpm_set_apu_thermal_limit() argument
514 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_apu_thermal_limit()
518 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_apu_thermal_limit()
519 ret = pp_funcs->set_apu_thermal_limit(adev->powerplay.pp_handle, limit); in amdgpu_dpm_set_apu_thermal_limit()
520 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_apu_thermal_limit()
526 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev) in amdgpu_dpm_compute_clocks() argument
528 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_compute_clocks()
531 if (!adev->pm.dpm_enabled) in amdgpu_dpm_compute_clocks()
537 if (adev->mode_info.num_crtc) in amdgpu_dpm_compute_clocks()
538 amdgpu_display_bandwidth_update(adev); in amdgpu_dpm_compute_clocks()
541 struct amdgpu_ring *ring = adev->rings[i]; in amdgpu_dpm_compute_clocks()
546 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
547 pp_funcs->pm_compute_clocks(adev->powerplay.pp_handle); in amdgpu_dpm_compute_clocks()
548 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_compute_clocks()
551 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_uvd() argument
555 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_uvd()
556 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
558 adev->pm.dpm.uvd_active = true; in amdgpu_dpm_enable_uvd()
559 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD; in amdgpu_dpm_enable_uvd()
561 adev->pm.dpm.uvd_active = false; in amdgpu_dpm_enable_uvd()
563 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_uvd()
565 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_uvd()
569 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); in amdgpu_dpm_enable_uvd()
575 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_vce() argument
579 if (adev->family == AMDGPU_FAMILY_SI) { in amdgpu_dpm_enable_vce()
580 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
582 adev->pm.dpm.vce_active = true; in amdgpu_dpm_enable_vce()
584 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL; in amdgpu_dpm_enable_vce()
586 adev->pm.dpm.vce_active = false; in amdgpu_dpm_enable_vce()
588 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_enable_vce()
590 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_enable_vce()
594 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); in amdgpu_dpm_enable_vce()
600 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_jpeg() argument
604 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_JPEG, !enable); in amdgpu_dpm_enable_jpeg()
610 void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_enable_vpe() argument
614 ret = amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VPE, !enable); in amdgpu_dpm_enable_vpe()
620 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version) in amdgpu_pm_load_smu_firmware() argument
622 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_pm_load_smu_firmware()
626 (is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU))) in amdgpu_pm_load_smu_firmware()
629 mutex_lock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
630 r = pp_funcs->load_firmware(adev->powerplay.pp_handle); in amdgpu_pm_load_smu_firmware()
637 *smu_version = adev->pm.fw_version; in amdgpu_pm_load_smu_firmware()
640 mutex_unlock(&adev->pm.mutex); in amdgpu_pm_load_smu_firmware()
644 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable) in amdgpu_dpm_handle_passthrough_sbr() argument
648 if (is_support_sw_smu(adev)) { in amdgpu_dpm_handle_passthrough_sbr()
649 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
650 ret = smu_handle_passthrough_sbr(adev->powerplay.pp_handle, in amdgpu_dpm_handle_passthrough_sbr()
652 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_handle_passthrough_sbr()
658 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_pages_num() argument
660 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_pages_num()
663 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_pages_num()
666 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
668 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_pages_num()
673 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size) in amdgpu_dpm_send_hbm_bad_channel_flag() argument
675 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_hbm_bad_channel_flag()
678 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_hbm_bad_channel_flag()
681 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
683 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_hbm_bad_channel_flag()
688 int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev) in amdgpu_dpm_send_rma_reason() argument
690 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_send_rma_reason()
693 if (!is_support_sw_smu(adev)) in amdgpu_dpm_send_rma_reason()
696 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_send_rma_reason()
698 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_send_rma_reason()
703 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_freq_range() argument
713 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_dpm_freq_range()
716 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
717 ret = smu_get_dpm_freq_range(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_freq_range()
721 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_freq_range()
726 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, in amdgpu_dpm_set_soft_freq_range() argument
731 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_soft_freq_range()
737 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_soft_freq_range()
740 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
745 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_soft_freq_range()
750 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev) in amdgpu_dpm_write_watermarks_table() argument
752 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_write_watermarks_table()
755 if (!is_support_sw_smu(adev)) in amdgpu_dpm_write_watermarks_table()
758 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
760 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_write_watermarks_table()
765 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, in amdgpu_dpm_wait_for_event() argument
769 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_wait_for_event()
772 if (!is_support_sw_smu(adev)) in amdgpu_dpm_wait_for_event()
775 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
777 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_wait_for_event()
782 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value) in amdgpu_dpm_set_residency_gfxoff() argument
784 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_set_residency_gfxoff()
787 if (!is_support_sw_smu(adev)) in amdgpu_dpm_set_residency_gfxoff()
790 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
792 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_residency_gfxoff()
797 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value) in amdgpu_dpm_get_residency_gfxoff() argument
799 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_residency_gfxoff()
802 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_residency_gfxoff()
805 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
807 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_residency_gfxoff()
812 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value) in amdgpu_dpm_get_entrycount_gfxoff() argument
814 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_entrycount_gfxoff()
817 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_entrycount_gfxoff()
820 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
822 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_entrycount_gfxoff()
827 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value) in amdgpu_dpm_get_status_gfxoff() argument
829 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_status_gfxoff()
832 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_status_gfxoff()
835 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
837 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_status_gfxoff()
842 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev) in amdgpu_dpm_get_thermal_throttling_counter() argument
844 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_thermal_throttling_counter()
846 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_thermal_throttling_counter()
857 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, in amdgpu_dpm_gfx_state_change() argument
860 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
861 if (adev->powerplay.pp_funcs && in amdgpu_dpm_gfx_state_change()
862 adev->powerplay.pp_funcs->gfx_state_change_set) in amdgpu_dpm_gfx_state_change()
863 ((adev)->powerplay.pp_funcs->gfx_state_change_set( in amdgpu_dpm_gfx_state_change()
864 (adev)->powerplay.pp_handle, state)); in amdgpu_dpm_gfx_state_change()
865 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_gfx_state_change()
868 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, in amdgpu_dpm_get_ecc_info() argument
871 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_ecc_info()
874 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_ecc_info()
877 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
879 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ecc_info()
884 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, in amdgpu_dpm_get_vce_clock_state() argument
887 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_vce_clock_state()
893 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
894 vstate = pp_funcs->get_vce_clock_state(adev->powerplay.pp_handle, in amdgpu_dpm_get_vce_clock_state()
896 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_vce_clock_state()
901 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, in amdgpu_dpm_get_current_power_state() argument
904 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_power_state()
906 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
909 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
913 *state = pp_funcs->get_current_power_state(adev->powerplay.pp_handle); in amdgpu_dpm_get_current_power_state()
916 *state = adev->pm.dpm.user_state; in amdgpu_dpm_get_current_power_state()
919 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_power_state()
922 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, in amdgpu_dpm_set_power_state() argument
925 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
926 adev->pm.dpm.user_state = state; in amdgpu_dpm_set_power_state()
927 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_state()
929 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_power_state()
932 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_power_state()
935 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_power_state()
938 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev) in amdgpu_dpm_get_performance_level() argument
940 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_performance_level()
946 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
948 level = pp_funcs->get_performance_level(adev->powerplay.pp_handle); in amdgpu_dpm_get_performance_level()
950 level = adev->pm.dpm.forced_level; in amdgpu_dpm_get_performance_level()
951 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_performance_level()
956 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_force_performance_level() argument
959 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_performance_level()
969 if (adev->pm.dpm.thermal_active) in amdgpu_dpm_force_performance_level()
972 current_level = amdgpu_dpm_get_performance_level(adev); in amdgpu_dpm_force_performance_level()
976 if (adev->asic_type == CHIP_RAVEN) { in amdgpu_dpm_force_performance_level()
977 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) { in amdgpu_dpm_force_performance_level()
980 amdgpu_gfx_off_ctrl(adev, false); in amdgpu_dpm_force_performance_level()
983 amdgpu_gfx_off_ctrl(adev, true); in amdgpu_dpm_force_performance_level()
994 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
997 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
1003 amdgpu_device_ip_set_clockgating_state(adev, in amdgpu_dpm_force_performance_level()
1006 amdgpu_device_ip_set_powergating_state(adev, in amdgpu_dpm_force_performance_level()
1011 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
1013 if (pp_funcs->force_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_performance_level()
1015 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
1019 adev->pm.dpm.forced_level = level; in amdgpu_dpm_force_performance_level()
1021 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_performance_level()
1026 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, in amdgpu_dpm_get_pp_num_states() argument
1029 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_num_states()
1035 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
1036 ret = pp_funcs->get_pp_num_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_num_states()
1038 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_num_states()
1043 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, in amdgpu_dpm_dispatch_task() argument
1047 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_dispatch_task()
1053 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
1054 ret = pp_funcs->dispatch_tasks(adev->powerplay.pp_handle, in amdgpu_dpm_dispatch_task()
1057 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_dispatch_task()
1062 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table) in amdgpu_dpm_get_pp_table() argument
1064 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pp_table()
1070 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
1071 ret = pp_funcs->get_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_pp_table()
1073 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pp_table()
1078 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, in amdgpu_dpm_set_fine_grain_clk_vol() argument
1083 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fine_grain_clk_vol()
1089 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
1090 ret = pp_funcs->set_fine_grain_clk_vol(adev->powerplay.pp_handle, in amdgpu_dpm_set_fine_grain_clk_vol()
1094 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fine_grain_clk_vol()
1099 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, in amdgpu_dpm_odn_edit_dpm_table() argument
1104 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_odn_edit_dpm_table()
1110 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1111 ret = pp_funcs->odn_edit_dpm_table(adev->powerplay.pp_handle, in amdgpu_dpm_odn_edit_dpm_table()
1115 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_odn_edit_dpm_table()
1120 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_print_clock_levels() argument
1124 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_print_clock_levels()
1130 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1131 ret = pp_funcs->print_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_print_clock_levels()
1134 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_print_clock_levels()
1139 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, in amdgpu_dpm_emit_clock_levels() argument
1144 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_emit_clock_levels()
1150 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1151 ret = pp_funcs->emit_clock_levels(adev->powerplay.pp_handle, in amdgpu_dpm_emit_clock_levels()
1155 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_emit_clock_levels()
1160 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, in amdgpu_dpm_set_ppfeature_status() argument
1163 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_ppfeature_status()
1169 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1170 ret = pp_funcs->set_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_set_ppfeature_status()
1172 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_ppfeature_status()
1177 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf) in amdgpu_dpm_get_ppfeature_status() argument
1179 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_ppfeature_status()
1185 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1186 ret = pp_funcs->get_ppfeature_status(adev->powerplay.pp_handle, in amdgpu_dpm_get_ppfeature_status()
1188 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_ppfeature_status()
1193 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, in amdgpu_dpm_force_clock_level() argument
1197 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_force_clock_level()
1203 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1204 ret = pp_funcs->force_clock_level(adev->powerplay.pp_handle, in amdgpu_dpm_force_clock_level()
1207 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_force_clock_level()
1212 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_sclk_od() argument
1214 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_sclk_od()
1220 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1221 ret = pp_funcs->get_sclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_sclk_od()
1222 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_sclk_od()
1227 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_sclk_od() argument
1229 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_sclk_od()
1231 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_sclk_od()
1234 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1236 pp_funcs->set_sclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_sclk_od()
1237 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_sclk_od()
1239 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_sclk_od()
1242 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_sclk_od()
1243 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_sclk_od()
1249 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev) in amdgpu_dpm_get_mclk_od() argument
1251 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_mclk_od()
1257 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1258 ret = pp_funcs->get_mclk_od(adev->powerplay.pp_handle); in amdgpu_dpm_get_mclk_od()
1259 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_mclk_od()
1264 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value) in amdgpu_dpm_set_mclk_od() argument
1266 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_mclk_od()
1268 if (is_support_sw_smu(adev)) in amdgpu_dpm_set_mclk_od()
1271 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1273 pp_funcs->set_mclk_od(adev->powerplay.pp_handle, value); in amdgpu_dpm_set_mclk_od()
1274 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_mclk_od()
1276 if (amdgpu_dpm_dispatch_task(adev, in amdgpu_dpm_set_mclk_od()
1279 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps; in amdgpu_dpm_set_mclk_od()
1280 amdgpu_dpm_compute_clocks(adev); in amdgpu_dpm_set_mclk_od()
1286 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_power_profile_mode() argument
1289 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_profile_mode()
1295 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1296 ret = pp_funcs->get_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_profile_mode()
1298 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_profile_mode()
1303 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_power_profile_mode() argument
1306 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_profile_mode()
1312 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1313 ret = pp_funcs->set_power_profile_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_profile_mode()
1316 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_profile_mode()
1321 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table) in amdgpu_dpm_get_gpu_metrics() argument
1323 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_gpu_metrics()
1329 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1330 ret = pp_funcs->get_gpu_metrics(adev->powerplay.pp_handle, in amdgpu_dpm_get_gpu_metrics()
1332 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_gpu_metrics()
1337 ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics, in amdgpu_dpm_get_pm_metrics() argument
1340 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_pm_metrics()
1346 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_pm_metrics()
1347 ret = pp_funcs->get_pm_metrics(adev->powerplay.pp_handle, pm_metrics, in amdgpu_dpm_get_pm_metrics()
1349 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_pm_metrics()
1354 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_control_mode() argument
1357 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_control_mode()
1363 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1364 ret = pp_funcs->get_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_control_mode()
1366 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_control_mode()
1371 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_pwm() argument
1374 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_pwm()
1380 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1381 ret = pp_funcs->set_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_pwm()
1383 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_pwm()
1388 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_pwm() argument
1391 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_pwm()
1397 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1398 ret = pp_funcs->get_fan_speed_pwm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_pwm()
1400 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_pwm()
1405 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_get_fan_speed_rpm() argument
1408 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_fan_speed_rpm()
1414 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1415 ret = pp_funcs->get_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_get_fan_speed_rpm()
1417 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_fan_speed_rpm()
1422 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_speed_rpm() argument
1425 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_speed_rpm()
1431 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1432 ret = pp_funcs->set_fan_speed_rpm(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_speed_rpm()
1434 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_speed_rpm()
1439 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, in amdgpu_dpm_set_fan_control_mode() argument
1442 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_fan_control_mode()
1448 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1449 ret = pp_funcs->set_fan_control_mode(adev->powerplay.pp_handle, in amdgpu_dpm_set_fan_control_mode()
1451 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_fan_control_mode()
1456 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_get_power_limit() argument
1461 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_power_limit()
1467 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1468 ret = pp_funcs->get_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_get_power_limit()
1472 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_power_limit()
1477 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, in amdgpu_dpm_set_power_limit() argument
1480 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_power_limit()
1486 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1487 ret = pp_funcs->set_power_limit(adev->powerplay.pp_handle, in amdgpu_dpm_set_power_limit()
1489 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_power_limit()
1494 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_cclk_dpm_supported() argument
1498 if (!is_support_sw_smu(adev)) in amdgpu_dpm_is_cclk_dpm_supported()
1501 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1502 cclk_dpm_supported = is_support_cclk_dpm(adev); in amdgpu_dpm_is_cclk_dpm_supported()
1503 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_is_cclk_dpm_supported()
1508 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, in amdgpu_dpm_debugfs_print_current_performance_level() argument
1511 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_debugfs_print_current_performance_level()
1516 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1517 pp_funcs->debugfs_print_current_performance_level(adev->powerplay.pp_handle, in amdgpu_dpm_debugfs_print_current_performance_level()
1519 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_debugfs_print_current_performance_level()
1524 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, in amdgpu_dpm_get_smu_prv_buf_details() argument
1528 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_smu_prv_buf_details()
1534 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1535 ret = pp_funcs->get_smu_prv_buf_details(adev->powerplay.pp_handle, in amdgpu_dpm_get_smu_prv_buf_details()
1538 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_smu_prv_buf_details()
1543 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev) in amdgpu_dpm_is_overdrive_supported() argument
1545 if (is_support_sw_smu(adev)) { in amdgpu_dpm_is_overdrive_supported()
1546 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1556 if (amdgpu_dpm_is_legacy_dpm(adev)) in amdgpu_dpm_is_overdrive_supported()
1559 hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle; in amdgpu_dpm_is_overdrive_supported()
1565 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, in amdgpu_dpm_set_pp_table() argument
1569 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_pp_table()
1575 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1576 ret = pp_funcs->set_pp_table(adev->powerplay.pp_handle, in amdgpu_dpm_set_pp_table()
1579 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_pp_table()
1584 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev) in amdgpu_dpm_get_num_cpu_cores() argument
1586 struct smu_context *smu = adev->powerplay.pp_handle; in amdgpu_dpm_get_num_cpu_cores()
1588 if (!is_support_sw_smu(adev)) in amdgpu_dpm_get_num_cpu_cores()
1594 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev) in amdgpu_dpm_stb_debug_fs_init() argument
1596 if (!is_support_sw_smu(adev)) in amdgpu_dpm_stb_debug_fs_init()
1599 amdgpu_smu_stb_debug_fs_init(adev); in amdgpu_dpm_stb_debug_fs_init()
1602 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, in amdgpu_dpm_display_configuration_change() argument
1605 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_configuration_change()
1611 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1612 ret = pp_funcs->display_configuration_change(adev->powerplay.pp_handle, in amdgpu_dpm_display_configuration_change()
1614 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_configuration_change()
1619 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type() argument
1623 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type()
1629 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1630 ret = pp_funcs->get_clock_by_type(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type()
1633 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type()
1638 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, in amdgpu_dpm_get_display_mode_validation_clks() argument
1641 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_display_mode_validation_clks()
1647 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1648 ret = pp_funcs->get_display_mode_validation_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_display_mode_validation_clks()
1650 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_display_mode_validation_clks()
1655 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_latency() argument
1659 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_latency()
1665 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1666 ret = pp_funcs->get_clock_by_type_with_latency(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_latency()
1669 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_latency()
1674 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, in amdgpu_dpm_get_clock_by_type_with_voltage() argument
1678 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_clock_by_type_with_voltage()
1684 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1685 ret = pp_funcs->get_clock_by_type_with_voltage(adev->powerplay.pp_handle, in amdgpu_dpm_get_clock_by_type_with_voltage()
1688 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_clock_by_type_with_voltage()
1693 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, in amdgpu_dpm_set_watermarks_for_clocks_ranges() argument
1696 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1702 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1703 ret = pp_funcs->set_watermarks_for_clocks_ranges(adev->powerplay.pp_handle, in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1705 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_watermarks_for_clocks_ranges()
1710 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, in amdgpu_dpm_display_clock_voltage_request() argument
1713 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_clock_voltage_request()
1719 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1720 ret = pp_funcs->display_clock_voltage_request(adev->powerplay.pp_handle, in amdgpu_dpm_display_clock_voltage_request()
1722 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_clock_voltage_request()
1727 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, in amdgpu_dpm_get_current_clocks() argument
1730 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_current_clocks()
1736 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1737 ret = pp_funcs->get_current_clocks(adev->powerplay.pp_handle, in amdgpu_dpm_get_current_clocks()
1739 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_current_clocks()
1744 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev) in amdgpu_dpm_notify_smu_enable_pwe() argument
1746 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_notify_smu_enable_pwe()
1751 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1752 pp_funcs->notify_smu_enable_pwe(adev->powerplay.pp_handle); in amdgpu_dpm_notify_smu_enable_pwe()
1753 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_notify_smu_enable_pwe()
1756 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, in amdgpu_dpm_set_active_display_count() argument
1759 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_active_display_count()
1765 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1766 ret = pp_funcs->set_active_display_count(adev->powerplay.pp_handle, in amdgpu_dpm_set_active_display_count()
1768 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_active_display_count()
1773 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, in amdgpu_dpm_set_min_deep_sleep_dcefclk() argument
1776 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1782 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1783 ret = pp_funcs->set_min_deep_sleep_dcefclk(adev->powerplay.pp_handle, in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1785 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_min_deep_sleep_dcefclk()
1790 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_dcefclk_by_freq() argument
1793 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1798 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1799 pp_funcs->set_hard_min_dcefclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1801 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_dcefclk_by_freq()
1804 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, in amdgpu_dpm_set_hard_min_fclk_by_freq() argument
1807 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_set_hard_min_fclk_by_freq()
1812 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1813 pp_funcs->set_hard_min_fclk_by_freq(adev->powerplay.pp_handle, in amdgpu_dpm_set_hard_min_fclk_by_freq()
1815 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_set_hard_min_fclk_by_freq()
1818 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, in amdgpu_dpm_display_disable_memory_clock_switch() argument
1821 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_display_disable_memory_clock_switch()
1827 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1828 ret = pp_funcs->display_disable_memory_clock_switch(adev->powerplay.pp_handle, in amdgpu_dpm_display_disable_memory_clock_switch()
1830 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_display_disable_memory_clock_switch()
1835 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, in amdgpu_dpm_get_max_sustainable_clocks_by_dc() argument
1838 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1844 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1845 ret = pp_funcs->get_max_sustainable_clocks_by_dc(adev->powerplay.pp_handle, in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1847 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_max_sustainable_clocks_by_dc()
1852 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, in amdgpu_dpm_get_uclk_dpm_states() argument
1856 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_uclk_dpm_states()
1862 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1863 ret = pp_funcs->get_uclk_dpm_states(adev->powerplay.pp_handle, in amdgpu_dpm_get_uclk_dpm_states()
1866 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_uclk_dpm_states()
1871 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, in amdgpu_dpm_get_dpm_clock_table() argument
1874 const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; in amdgpu_dpm_get_dpm_clock_table()
1880 mutex_lock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()
1881 ret = pp_funcs->get_dpm_clock_table(adev->powerplay.pp_handle, in amdgpu_dpm_get_dpm_clock_table()
1883 mutex_unlock(&adev->pm.mutex); in amdgpu_dpm_get_dpm_clock_table()