Lines Matching refs:gpu_write
477 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
479 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
536 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
539 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
544 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
552 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
556 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
579 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
671 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address); in etnaviv_gpu_start_fe()
672 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
677 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL, in etnaviv_gpu_start_fe()
752 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug); in etnaviv_gpu_hw_init()
762 gpu_write(gpu, VIVS_HI_AXI_CONFIG, in etnaviv_gpu_hw_init()
773 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config); in etnaviv_gpu_hw_init()
779 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val); in etnaviv_gpu_hw_init()
785 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U); in etnaviv_gpu_hw_init()
1341 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_pre()
1364 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val); in sync_point_perfmon_sample_post()