Lines Matching refs:dev_priv
124 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_get_cdclk() argument
127 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
130 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, in intel_cdclk_set_cdclk() argument
134 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
139 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_cdclk_modeset_calc_cdclk() local
141 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); in intel_cdclk_modeset_calc_cdclk()
144 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, in intel_cdclk_calc_voltage_level() argument
147 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
150 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_133mhz_get_cdclk() argument
156 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_200mhz_get_cdclk() argument
162 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_266mhz_get_cdclk() argument
168 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_333mhz_get_cdclk() argument
174 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_400mhz_get_cdclk() argument
180 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv, in fixed_450mhz_get_cdclk() argument
186 static void i85x_get_cdclk(struct drm_i915_private *dev_priv, in i85x_get_cdclk() argument
189 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
228 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv, in i915gm_get_cdclk() argument
231 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
252 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv, in i945gm_get_cdclk() argument
255 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
276 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv) in intel_hpll_vco() argument
320 if (IS_GM45(dev_priv)) in intel_hpll_vco()
322 else if (IS_G45(dev_priv)) in intel_hpll_vco()
324 else if (IS_I965GM(dev_priv)) in intel_hpll_vco()
326 else if (IS_PINEVIEW(dev_priv)) in intel_hpll_vco()
328 else if (IS_G33(dev_priv)) in intel_hpll_vco()
333 tmp = intel_de_read(dev_priv, in intel_hpll_vco()
334 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
338 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
341 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
346 static void g33_get_cdclk(struct drm_i915_private *dev_priv, in g33_get_cdclk() argument
349 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
358 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
389 drm_err(&dev_priv->drm, in g33_get_cdclk()
395 static void pnv_get_cdclk(struct drm_i915_private *dev_priv, in pnv_get_cdclk() argument
398 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
417 drm_err(&dev_priv->drm, in pnv_get_cdclk()
429 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv, in i965gm_get_cdclk() argument
432 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
440 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
468 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
474 static void gm45_get_cdclk(struct drm_i915_private *dev_priv, in gm45_get_cdclk() argument
477 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
481 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
497 drm_err(&dev_priv->drm, in gm45_get_cdclk()
505 static void hsw_get_cdclk(struct drm_i915_private *dev_priv, in hsw_get_cdclk() argument
508 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk()
513 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
517 else if (IS_HASWELL_ULT(dev_priv)) in hsw_get_cdclk()
523 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in vlv_calc_cdclk() argument
525 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
533 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320) in vlv_calc_cdclk()
543 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk) in vlv_calc_voltage_level() argument
545 if (IS_VALLEYVIEW(dev_priv)) { in vlv_calc_voltage_level()
558 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
562 static void vlv_get_cdclk(struct drm_i915_private *dev_priv, in vlv_get_cdclk() argument
567 vlv_iosf_sb_get(dev_priv, in vlv_get_cdclk()
570 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
571 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
575 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
577 vlv_iosf_sb_put(dev_priv, in vlv_get_cdclk()
580 if (IS_VALLEYVIEW(dev_priv)) in vlv_get_cdclk()
588 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) in vlv_program_pfi_credits() argument
592 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
597 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
599 if (IS_CHERRYVIEW(dev_priv)) in vlv_program_pfi_credits()
611 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
614 intel_de_write(dev_priv, GCI_CONTROL, in vlv_program_pfi_credits()
621 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
622 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
625 static void vlv_set_cdclk(struct drm_i915_private *dev_priv, in vlv_set_cdclk() argument
651 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in vlv_set_cdclk()
653 vlv_iosf_sb_get(dev_priv, in vlv_set_cdclk()
658 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
661 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
662 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
665 drm_err(&dev_priv->drm, in vlv_set_cdclk()
672 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
676 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); in vlv_set_cdclk()
679 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); in vlv_set_cdclk()
681 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
684 drm_err(&dev_priv->drm, in vlv_set_cdclk()
689 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); in vlv_set_cdclk()
700 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); in vlv_set_cdclk()
702 vlv_iosf_sb_put(dev_priv, in vlv_set_cdclk()
707 intel_update_cdclk(dev_priv); in vlv_set_cdclk()
709 vlv_program_pfi_credits(dev_priv); in vlv_set_cdclk()
711 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in vlv_set_cdclk()
714 static void chv_set_cdclk(struct drm_i915_private *dev_priv, in chv_set_cdclk() argument
739 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE); in chv_set_cdclk()
741 vlv_punit_get(dev_priv); in chv_set_cdclk()
742 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
745 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
746 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
749 drm_err(&dev_priv->drm, in chv_set_cdclk()
753 vlv_punit_put(dev_priv); in chv_set_cdclk()
755 intel_update_cdclk(dev_priv); in chv_set_cdclk()
757 vlv_program_pfi_credits(dev_priv); in chv_set_cdclk()
759 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref); in chv_set_cdclk()
789 static void bdw_get_cdclk(struct drm_i915_private *dev_priv, in bdw_get_cdclk() argument
792 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk()
797 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
833 static void bdw_set_cdclk(struct drm_i915_private *dev_priv, in bdw_set_cdclk() argument
840 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
841 (intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
849 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
851 drm_err(&dev_priv->drm, in bdw_set_cdclk()
856 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
863 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
865 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
867 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
870 intel_de_rmw(dev_priv, LCPLL_CTL, in bdw_set_cdclk()
873 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) & in bdw_set_cdclk()
875 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
877 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
880 intel_de_write(dev_priv, CDCLK_FREQ, in bdw_set_cdclk()
883 intel_update_cdclk(dev_priv); in bdw_set_cdclk()
921 static void skl_dpll0_update(struct drm_i915_private *dev_priv, in skl_dpll0_update() argument
929 val = intel_de_read(dev_priv, LCPLL1_CTL); in skl_dpll0_update()
933 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
936 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_dpll0_update()
938 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
962 static void skl_get_cdclk(struct drm_i915_private *dev_priv, in skl_get_cdclk() argument
967 skl_dpll0_update(dev_priv, cdclk_config); in skl_get_cdclk()
974 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_get_cdclk()
1039 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_link_rate() argument
1041 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1058 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) in skl_dpll0_enable() argument
1060 intel_de_rmw(dev_priv, DPLL_CTRL1, in skl_dpll0_enable()
1065 skl_dpll0_link_rate(dev_priv, vco)); in skl_dpll0_enable()
1066 intel_de_posting_read(dev_priv, DPLL_CTRL1); in skl_dpll0_enable()
1068 intel_de_rmw(dev_priv, LCPLL1_CTL, in skl_dpll0_enable()
1071 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1072 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1074 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1077 skl_set_preferred_cdclk_vco(dev_priv, vco); in skl_dpll0_enable()
1080 static void skl_dpll0_disable(struct drm_i915_private *dev_priv) in skl_dpll0_disable() argument
1082 intel_de_rmw(dev_priv, LCPLL1_CTL, in skl_dpll0_disable()
1085 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1)) in skl_dpll0_disable()
1086 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1088 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1091 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv, in skl_cdclk_freq_sel() argument
1096 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1097 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1098 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1114 static void skl_set_cdclk(struct drm_i915_private *dev_priv, in skl_set_cdclk() argument
1131 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1132 IS_SKYLAKE(dev_priv) && vco == 8640000); in skl_set_cdclk()
1134 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1139 drm_err(&dev_priv->drm, in skl_set_cdclk()
1144 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco); in skl_set_cdclk()
1146 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1147 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1148 skl_dpll0_disable(dev_priv); in skl_set_cdclk()
1150 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1152 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1156 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1161 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1162 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1164 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1165 skl_dpll0_enable(dev_priv, vco); in skl_set_cdclk()
1169 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1172 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1176 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl); in skl_set_cdclk()
1177 intel_de_posting_read(dev_priv, CDCLK_CTL); in skl_set_cdclk()
1180 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1183 intel_update_cdclk(dev_priv); in skl_set_cdclk()
1186 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv) in skl_sanitize_cdclk() argument
1195 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0) in skl_sanitize_cdclk()
1198 intel_update_cdclk(dev_priv); in skl_sanitize_cdclk()
1199 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1202 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1203 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1212 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in skl_sanitize_cdclk()
1214 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1220 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1223 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1225 dev_priv->display.cdclk.hw.vco = ~0; in skl_sanitize_cdclk()
1228 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv) in skl_cdclk_init_hw() argument
1232 skl_sanitize_cdclk(dev_priv); in skl_cdclk_init_hw()
1234 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1235 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1240 if (dev_priv->display.cdclk.skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1241 skl_set_preferred_cdclk_vco(dev_priv, in skl_cdclk_init_hw()
1242 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1246 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1248 cdclk_config.vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_cdclk_init_hw()
1254 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1257 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in skl_cdclk_uninit_hw() argument
1259 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1265 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1473 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk) in bxt_calc_cdclk() argument
1475 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1479 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1483 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1485 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1489 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk) in bxt_calc_cdclk_pll_vco() argument
1491 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1494 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1498 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1500 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1502 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1503 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1585 static void icl_readout_refclk(struct drm_i915_private *dev_priv, in icl_readout_refclk() argument
1588 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK; in icl_readout_refclk()
1606 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv, in bxt_de_pll_readout() argument
1611 if (IS_DG2(dev_priv)) in bxt_de_pll_readout()
1613 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1614 icl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1618 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE); in bxt_de_pll_readout()
1633 if (DISPLAY_VER(dev_priv) >= 11) in bxt_de_pll_readout()
1636 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; in bxt_de_pll_readout()
1641 static void bxt_get_cdclk(struct drm_i915_private *dev_priv, in bxt_get_cdclk() argument
1648 bxt_de_pll_readout(dev_priv, cdclk_config); in bxt_get_cdclk()
1650 if (DISPLAY_VER(dev_priv) >= 12) in bxt_get_cdclk()
1652 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_get_cdclk()
1662 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK; in bxt_get_cdclk()
1682 if (HAS_CDCLK_SQUASH(dev_priv)) in bxt_get_cdclk()
1683 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL); in bxt_get_cdclk()
1699 if (DISPLAY_VER(dev_priv) >= 20) in bxt_get_cdclk()
1700 cdclk_config->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN; in bxt_get_cdclk()
1706 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1709 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv) in bxt_de_pll_disable() argument
1711 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0); in bxt_de_pll_disable()
1714 if (intel_de_wait_for_clear(dev_priv, in bxt_de_pll_disable()
1716 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1718 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1721 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco) in bxt_de_pll_enable() argument
1723 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1725 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL, in bxt_de_pll_enable()
1728 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); in bxt_de_pll_enable()
1731 if (intel_de_wait_for_set(dev_priv, in bxt_de_pll_enable()
1733 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1735 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1738 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv) in icl_cdclk_pll_disable() argument
1740 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE, in icl_cdclk_pll_disable()
1744 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_disable()
1745 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1747 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1750 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) in icl_cdclk_pll_enable() argument
1752 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1756 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1759 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in icl_cdclk_pll_enable()
1762 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1763 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1765 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1768 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco) in adlp_cdclk_pll_crawl() argument
1770 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1775 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1779 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1782 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
1784 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1787 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val); in adlp_cdclk_pll_crawl()
1789 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1792 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) in bxt_cdclk_cd2x_pipe() argument
1794 if (DISPLAY_VER(dev_priv) >= 12) { in bxt_cdclk_cd2x_pipe()
1799 } else if (DISPLAY_VER(dev_priv) >= 11) { in bxt_cdclk_cd2x_pipe()
1812 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv, in bxt_cdclk_cd2x_div_sel() argument
1818 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1819 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1820 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1833 static u16 cdclk_squash_waveform(struct drm_i915_private *dev_priv, in cdclk_squash_waveform() argument
1836 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1839 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1843 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1847 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1848 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1999 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) in pll_enable_wa_needed() argument
2001 return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) || in pll_enable_wa_needed()
2002 DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) || in pll_enable_wa_needed()
2003 IS_DG2(dev_priv)) && in pll_enable_wa_needed()
2004 dev_priv->display.cdclk.hw.vco > 0; in pll_enable_wa_needed()
2037 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, in _bxt_set_cdclk() argument
2044 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
2045 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
2046 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
2047 adlp_cdclk_pll_crawl(dev_priv, vco); in _bxt_set_cdclk()
2048 } else if (DISPLAY_VER(dev_priv) >= 11) { in _bxt_set_cdclk()
2050 if (pll_enable_wa_needed(dev_priv)) in _bxt_set_cdclk()
2051 dg2_cdclk_squash_program(dev_priv, 0); in _bxt_set_cdclk()
2053 icl_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
2055 bxt_cdclk_pll_update(dev_priv, vco); in _bxt_set_cdclk()
2057 if (HAS_CDCLK_SQUASH(dev_priv)) { in _bxt_set_cdclk()
2058 u16 waveform = cdclk_squash_waveform(dev_priv, cdclk); in _bxt_set_cdclk()
2060 dg2_cdclk_squash_program(dev_priv, waveform); in _bxt_set_cdclk()
2063 intel_de_write(dev_priv, CDCLK_CTL, bxt_cdclk_ctl(dev_priv, cdclk_config, pipe)); in _bxt_set_cdclk()
2066 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); in _bxt_set_cdclk()
2069 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, in bxt_set_cdclk() argument
2083 if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv)) in bxt_set_cdclk()
2085 else if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
2086 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2095 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2100 drm_err(&dev_priv->drm, in bxt_set_cdclk()
2106 if (DISPLAY_VER(dev_priv) >= 20 && cdclk < dev_priv->display.cdclk.hw.cdclk) in bxt_set_cdclk()
2107 xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); in bxt_set_cdclk()
2109 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
2111 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe); in bxt_set_cdclk()
2112 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
2114 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
2117 if (DISPLAY_VER(dev_priv) >= 20 && cdclk > dev_priv->display.cdclk.hw.cdclk) in bxt_set_cdclk()
2118 xe2lpd_mdclk_cdclk_ratio_program(dev_priv, cdclk_config); in bxt_set_cdclk()
2120 if (DISPLAY_VER(dev_priv) >= 14) in bxt_set_cdclk()
2125 else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv)) in bxt_set_cdclk()
2126 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
2128 if (DISPLAY_VER(dev_priv) < 11) { in bxt_set_cdclk()
2135 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
2141 drm_err(&dev_priv->drm, in bxt_set_cdclk()
2147 intel_update_cdclk(dev_priv); in bxt_set_cdclk()
2149 if (DISPLAY_VER(dev_priv) >= 11) in bxt_set_cdclk()
2154 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2157 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv) in bxt_sanitize_cdclk() argument
2162 intel_update_cdclk(dev_priv); in bxt_sanitize_cdclk()
2163 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
2165 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
2166 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
2170 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2171 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2175 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_sanitize_cdclk()
2176 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2184 cdctl = intel_de_read(dev_priv, CDCLK_CTL); in bxt_sanitize_cdclk()
2185 expected = bxt_cdclk_ctl(dev_priv, &dev_priv->display.cdclk.hw, INVALID_PIPE); in bxt_sanitize_cdclk()
2192 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); in bxt_sanitize_cdclk()
2193 expected &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE); in bxt_sanitize_cdclk()
2200 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2203 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2206 dev_priv->display.cdclk.hw.vco = ~0; in bxt_sanitize_cdclk()
2209 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_init_hw() argument
2213 bxt_sanitize_cdclk(dev_priv); in bxt_cdclk_init_hw()
2215 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2216 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2219 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2226 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2227 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2229 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2231 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2234 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) in bxt_cdclk_uninit_hw() argument
2236 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2241 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2243 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2300 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, in intel_cdclk_can_crawl() argument
2306 if (!HAS_CDCLK_CRAWL(dev_priv)) in intel_cdclk_can_crawl()
2322 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv, in intel_cdclk_can_squash() argument
2332 if (!HAS_CDCLK_SQUASH(dev_priv)) in intel_cdclk_can_squash()
2369 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv, in intel_cdclk_can_cd2x_update() argument
2374 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv)) in intel_cdclk_can_cd2x_update()
2383 if (HAS_CDCLK_SQUASH(dev_priv)) in intel_cdclk_can_cd2x_update()
2449 static void intel_set_cdclk(struct drm_i915_private *dev_priv, in intel_set_cdclk() argument
2455 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2458 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2461 intel_cdclk_dump_config(dev_priv, cdclk_config, context); in intel_set_cdclk()
2463 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2469 intel_audio_cdclk_change_pre(dev_priv); in intel_set_cdclk()
2476 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2477 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2481 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2484 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
2486 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2491 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2493 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2499 intel_audio_cdclk_change_post(dev_priv); in intel_set_cdclk()
2501 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2502 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2504 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2505 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); in intel_set_cdclk()
2693 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk() local
2696 if (DISPLAY_VER(dev_priv) >= 10) in intel_pixel_rate_to_cdclk()
2698 else if (DISPLAY_VER(dev_priv) == 9 || in intel_pixel_rate_to_cdclk()
2699 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2701 else if (IS_CHERRYVIEW(dev_priv)) in intel_pixel_rate_to_cdclk()
2712 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk() local
2716 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2767 struct drm_i915_private *dev_priv = in intel_crtc_compute_min_cdclk() local
2777 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state)) in intel_crtc_compute_min_cdclk()
2789 if (DISPLAY_VER(dev_priv) == 10) { in intel_crtc_compute_min_cdclk()
2792 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) { in intel_crtc_compute_min_cdclk()
2802 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2812 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && in intel_crtc_compute_min_cdclk()
2821 IS_VALLEYVIEW(dev_priv)) in intel_crtc_compute_min_cdclk()
2830 IS_GEMINILAKE(dev_priv)) in intel_crtc_compute_min_cdclk()
2844 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk() local
2872 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state); in intel_compute_min_cdclk()
2887 for_each_pipe(dev_priv, pipe) in intel_compute_min_cdclk()
2898 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2902 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2903 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2905 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2927 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level() local
2955 for_each_pipe(dev_priv, pipe) in bxt_compute_min_voltage_level()
2964 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk() local
2973 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk); in vlv_modeset_calc_cdclk()
2977 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
2980 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2984 vlv_calc_voltage_level(dev_priv, cdclk); in vlv_modeset_calc_cdclk()
3023 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco() local
3032 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in skl_dpll0_vco()
3094 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk() local
3107 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk); in bxt_modeset_calc_cdclk()
3108 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3114 intel_cdclk_calc_voltage_level(dev_priv, cdclk)); in bxt_modeset_calc_cdclk()
3117 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
3118 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3123 intel_cdclk_calc_voltage_level(dev_priv, cdclk); in bxt_modeset_calc_cdclk()
3175 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state() local
3178 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3234 int intel_cdclk_init(struct drm_i915_private *dev_priv) in intel_cdclk_init() argument
3242 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3265 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk() local
3284 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { in intel_modeset_calc_cdclk()
3304 intel_cdclk_can_cd2x_update(dev_priv, in intel_modeset_calc_cdclk()
3311 crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_modeset_calc_cdclk()
3321 if (intel_cdclk_can_crawl_and_squash(dev_priv, in intel_modeset_calc_cdclk()
3324 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3326 } else if (intel_cdclk_can_squash(dev_priv, in intel_modeset_calc_cdclk()
3329 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3331 } else if (intel_cdclk_can_crawl(dev_priv, in intel_modeset_calc_cdclk()
3334 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3339 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3351 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3355 if (intel_mdclk_cdclk_ratio(dev_priv, &old_cdclk_state->actual) != in intel_modeset_calc_cdclk()
3356 intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3357 int ratio = intel_mdclk_cdclk_ratio(dev_priv, &new_cdclk_state->actual); in intel_modeset_calc_cdclk()
3364 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3368 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3376 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) in intel_compute_max_dotclk() argument
3378 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3380 if (DISPLAY_VER(dev_priv) >= 10) in intel_compute_max_dotclk()
3382 else if (DISPLAY_VER(dev_priv) == 9 || in intel_compute_max_dotclk()
3383 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
3385 else if (IS_CHERRYVIEW(dev_priv)) in intel_compute_max_dotclk()
3387 else if (DISPLAY_VER(dev_priv) < 4) in intel_compute_max_dotclk()
3401 void intel_update_max_cdclk(struct drm_i915_private *dev_priv) in intel_update_max_cdclk() argument
3403 if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in intel_update_max_cdclk()
3404 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3405 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3407 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3408 } else if (DISPLAY_VER(dev_priv) >= 11) { in intel_update_max_cdclk()
3409 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3410 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3412 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3413 } else if (IS_GEMINILAKE(dev_priv)) { in intel_update_max_cdclk()
3414 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3415 } else if (IS_BROXTON(dev_priv)) { in intel_update_max_cdclk()
3416 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3417 } else if (DISPLAY_VER(dev_priv) == 9) { in intel_update_max_cdclk()
3418 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; in intel_update_max_cdclk()
3421 vco = dev_priv->display.cdclk.skl_preferred_vco_freq; in intel_update_max_cdclk()
3422 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3438 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3439 } else if (IS_BROADWELL(dev_priv)) { in intel_update_max_cdclk()
3446 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT) in intel_update_max_cdclk()
3447 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3448 else if (IS_BROADWELL_ULX(dev_priv)) in intel_update_max_cdclk()
3449 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3450 else if (IS_BROADWELL_ULT(dev_priv)) in intel_update_max_cdclk()
3451 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3453 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3454 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_update_max_cdclk()
3455 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3456 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_update_max_cdclk()
3457 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3460 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3463 dev_priv->display.cdclk.max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3465 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3466 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3468 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3469 dev_priv->display.cdclk.max_dotclk_freq); in intel_update_max_cdclk()
3478 void intel_update_cdclk(struct drm_i915_private *dev_priv) in intel_update_cdclk() argument
3480 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3488 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
3489 intel_de_write(dev_priv, GMBUSFREQ_VLV, in intel_update_cdclk()
3490 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3493 static int dg1_rawclk(struct drm_i915_private *dev_priv) in dg1_rawclk() argument
3499 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, in dg1_rawclk()
3505 static int cnp_rawclk(struct drm_i915_private *dev_priv) in cnp_rawclk() argument
3510 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) { in cnp_rawclk()
3526 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) in cnp_rawclk()
3530 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk); in cnp_rawclk()
3534 static int pch_rawclk(struct drm_i915_private *dev_priv) in pch_rawclk() argument
3536 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; in pch_rawclk()
3539 static int vlv_hrawclk(struct drm_i915_private *dev_priv) in vlv_hrawclk() argument
3542 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", in vlv_hrawclk()
3559 u32 intel_read_rawclk(struct drm_i915_private *dev_priv) in intel_read_rawclk() argument
3563 if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) in intel_read_rawclk()
3570 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) in intel_read_rawclk()
3571 freq = dg1_rawclk(dev_priv); in intel_read_rawclk()
3572 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) in intel_read_rawclk()
3573 freq = cnp_rawclk(dev_priv); in intel_read_rawclk()
3574 else if (HAS_PCH_SPLIT(dev_priv)) in intel_read_rawclk()
3575 freq = pch_rawclk(dev_priv); in intel_read_rawclk()
3576 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_read_rawclk()
3577 freq = vlv_hrawclk(dev_priv); in intel_read_rawclk()
3578 else if (DISPLAY_VER(dev_priv) >= 3) in intel_read_rawclk()
3579 freq = i9xx_hrawclk(dev_priv); in intel_read_rawclk()
3748 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) in intel_init_cdclk_hooks() argument
3750 if (DISPLAY_VER(dev_priv) >= 20) { in intel_init_cdclk_hooks()
3751 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3752 dev_priv->display.cdclk.table = xe2lpd_cdclk_table; in intel_init_cdclk_hooks()
3753 } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { in intel_init_cdclk_hooks()
3754 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3755 dev_priv->display.cdclk.table = xe2hpd_cdclk_table; in intel_init_cdclk_hooks()
3756 } else if (DISPLAY_VER(dev_priv) >= 14) { in intel_init_cdclk_hooks()
3757 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3758 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3759 } else if (IS_DG2(dev_priv)) { in intel_init_cdclk_hooks()
3760 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3761 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3762 } else if (IS_ALDERLAKE_P(dev_priv)) { in intel_init_cdclk_hooks()
3764 if (IS_ALDERLAKE_P(dev_priv) && IS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) { in intel_init_cdclk_hooks()
3765 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3766 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3767 } else if (IS_RAPTORLAKE_U(dev_priv)) { in intel_init_cdclk_hooks()
3768 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3769 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3771 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3772 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3774 } else if (IS_ROCKETLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3775 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3776 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3777 } else if (DISPLAY_VER(dev_priv) >= 12) { in intel_init_cdclk_hooks()
3778 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3779 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3780 } else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3781 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3782 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3783 } else if (DISPLAY_VER(dev_priv) >= 11) { in intel_init_cdclk_hooks()
3784 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3785 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3786 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { in intel_init_cdclk_hooks()
3787 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3788 if (IS_GEMINILAKE(dev_priv)) in intel_init_cdclk_hooks()
3789 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3791 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3792 } else if (DISPLAY_VER(dev_priv) == 9) { in intel_init_cdclk_hooks()
3793 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3794 } else if (IS_BROADWELL(dev_priv)) { in intel_init_cdclk_hooks()
3795 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3796 } else if (IS_HASWELL(dev_priv)) { in intel_init_cdclk_hooks()
3797 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3798 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3799 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3800 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3801 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3802 } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) { in intel_init_cdclk_hooks()
3803 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3804 } else if (IS_IRONLAKE(dev_priv)) { in intel_init_cdclk_hooks()
3805 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3806 } else if (IS_GM45(dev_priv)) { in intel_init_cdclk_hooks()
3807 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3808 } else if (IS_G45(dev_priv)) { in intel_init_cdclk_hooks()
3809 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3810 } else if (IS_I965GM(dev_priv)) { in intel_init_cdclk_hooks()
3811 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3812 } else if (IS_I965G(dev_priv)) { in intel_init_cdclk_hooks()
3813 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3814 } else if (IS_PINEVIEW(dev_priv)) { in intel_init_cdclk_hooks()
3815 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3816 } else if (IS_G33(dev_priv)) { in intel_init_cdclk_hooks()
3817 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3818 } else if (IS_I945GM(dev_priv)) { in intel_init_cdclk_hooks()
3819 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3820 } else if (IS_I945G(dev_priv)) { in intel_init_cdclk_hooks()
3821 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3822 } else if (IS_I915GM(dev_priv)) { in intel_init_cdclk_hooks()
3823 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3824 } else if (IS_I915G(dev_priv)) { in intel_init_cdclk_hooks()
3825 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3826 } else if (IS_I865G(dev_priv)) { in intel_init_cdclk_hooks()
3827 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3828 } else if (IS_I85X(dev_priv)) { in intel_init_cdclk_hooks()
3829 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3830 } else if (IS_I845G(dev_priv)) { in intel_init_cdclk_hooks()
3831 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3832 } else if (IS_I830(dev_priv)) { in intel_init_cdclk_hooks()
3833 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3836 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3838 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()