Lines Matching refs:display
20 struct intel_display *display = to_intel_display(connector); in intel_vrr_is_capable() local
46 return HAS_VRR(display) && in intel_vrr_is_capable()
92 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_vblank_exit_length() local
94 if (DISPLAY_VER(display) >= 13) in intel_vrr_vblank_exit_length()
115 struct intel_display *display = to_intel_display(crtc_state); in is_cmrr_frac_required() local
119 if (!HAS_CMRR(display)) in is_cmrr_frac_required()
163 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_compute_config() local
187 if (HAS_LRR(display)) in intel_vrr_compute_config()
247 if (DISPLAY_VER(display) >= 13) { in intel_vrr_compute_config()
259 struct intel_display *display = to_intel_display(crtc_state); in trans_vrr_ctl() local
261 if (DISPLAY_VER(display) >= 13) in trans_vrr_ctl()
272 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_set_transcoder_timings() local
280 if (IS_DISPLAY_VER(display, 12, 13)) in intel_vrr_set_transcoder_timings()
281 intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder), in intel_vrr_set_transcoder_timings()
285 intel_de_write(display, in intel_vrr_set_transcoder_timings()
286 TRANS_VRR_CTL(display, cpu_transcoder), 0); in intel_vrr_set_transcoder_timings()
291 intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
293 intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
295 intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
297 intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
301 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
303 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
305 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
307 intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
313 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_send_push() local
319 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_send_push()
325 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_is_push_sent() local
331 return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; in intel_vrr_is_push_sent()
336 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_enable() local
342 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_enable()
345 if (HAS_AS_SDP(display)) in intel_vrr_enable()
346 intel_de_write(display, in intel_vrr_enable()
347 TRANS_VRR_VSYNC(display, cpu_transcoder), in intel_vrr_enable()
352 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
356 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
363 struct intel_display *display = to_intel_display(old_crtc_state); in intel_vrr_disable() local
369 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_disable()
371 intel_de_wait_for_clear(display, in intel_vrr_disable()
372 TRANS_VRR_STATUS(display, cpu_transcoder), in intel_vrr_disable()
374 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); in intel_vrr_disable()
376 if (HAS_AS_SDP(display)) in intel_vrr_disable()
377 intel_de_write(display, in intel_vrr_disable()
378 TRANS_VRR_VSYNC(display, cpu_transcoder), 0); in intel_vrr_disable()
383 struct intel_display *display = to_intel_display(crtc_state); in intel_vrr_get_config() local
387 trans_vrr_ctl = intel_de_read(display, in intel_vrr_get_config()
388 TRANS_VRR_CTL(display, cpu_transcoder)); in intel_vrr_get_config()
391 if (HAS_CMRR(display)) in intel_vrr_get_config()
396 intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder), in intel_vrr_get_config()
397 TRANS_CMRR_N_HI(display, cpu_transcoder)); in intel_vrr_get_config()
399 intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder), in intel_vrr_get_config()
400 TRANS_CMRR_M_HI(display, cpu_transcoder)); in intel_vrr_get_config()
403 if (DISPLAY_VER(display) >= 13) in intel_vrr_get_config()
412 crtc_state->vrr.flipline = intel_de_read(display, in intel_vrr_get_config()
413 TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1; in intel_vrr_get_config()
414 crtc_state->vrr.vmax = intel_de_read(display, in intel_vrr_get_config()
415 TRANS_VRR_VMAX(display, cpu_transcoder)) + 1; in intel_vrr_get_config()
416 crtc_state->vrr.vmin = intel_de_read(display, in intel_vrr_get_config()
417 TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; in intel_vrr_get_config()
423 if (HAS_AS_SDP(display)) { in intel_vrr_get_config()
425 intel_de_read(display, in intel_vrr_get_config()
426 TRANS_VRR_VSYNC(display, cpu_transcoder)); in intel_vrr_get_config()