Lines Matching refs:pvr_dev
34 process_elf_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr, in process_elf_command_stream() argument
39 struct drm_device *drm_dev = from_pvr_device(pvr_dev); in process_elf_command_stream()
50 err = pvr_fw_find_mmu_segment(pvr_dev, program_header->p_vaddr, in process_elf_command_stream()
74 pvr_mips_init(struct pvr_device *pvr_dev) in pvr_mips_init() argument
76 pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_MIPS_SHIFT, ROGUE_FW_HEAP_MIPS_RESERVED_SIZE); in pvr_mips_init()
78 return pvr_vm_mips_init(pvr_dev); in pvr_mips_init()
82 pvr_mips_fini(struct pvr_device *pvr_dev) in pvr_mips_fini() argument
84 pvr_vm_mips_fini(pvr_dev); in pvr_mips_fini()
88 pvr_mips_fw_process(struct pvr_device *pvr_dev, const u8 *fw, in pvr_mips_fw_process() argument
92 struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev; in pvr_mips_fw_process()
103 err = process_elf_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, fw_core_code_ptr, in pvr_mips_fw_process()
108 boot_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_CODE); in pvr_mips_fw_process()
109 boot_data_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_BOOT_DATA); in pvr_mips_fw_process()
110 exception_code_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_EXCEPTIONS_CODE); in pvr_mips_fw_process()
122 stack_entry = pvr_fw_find_layout_entry(pvr_dev, MIPS_STACK); in pvr_mips_fw_process()
133 boot_data->reg_base = pvr_dev->regs_resource->start; in pvr_mips_fw_process()
153 pvr_mips_wrapper_init(struct pvr_device *pvr_dev) in pvr_mips_wrapper_init() argument
155 struct pvr_fw_mips_data *mips_data = pvr_dev->fw_dev.processor_data.mips_data; in pvr_mips_wrapper_init()
159 int err = PVR_FEATURE_VALUE(pvr_dev, phys_bus_width, &phys_bus_width); in pvr_mips_wrapper_init()
168 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_WRAPPER_CONFIG, in pvr_mips_wrapper_init()
174 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1, in pvr_mips_wrapper_init()
177 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2, in pvr_mips_wrapper_init()
181 if (PVR_HAS_QUIRK(pvr_dev, 63553)) { in pvr_mips_wrapper_init()
188 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1, in pvr_mips_wrapper_init()
190 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2, in pvr_mips_wrapper_init()
196 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1, in pvr_mips_wrapper_init()
199 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2, in pvr_mips_wrapper_init()
203 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1, in pvr_mips_wrapper_init()
206 pvr_cr_write64(pvr_dev, ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2, in pvr_mips_wrapper_init()
211 pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, in pvr_mips_wrapper_init()
215 pvr_cr_write32(pvr_dev, ROGUE_CR_MIPS_DEBUG_CONFIG, 0); in pvr_mips_wrapper_init()
223 struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev); in pvr_mips_get_fw_addr_with_offset() local
226 return ((fw_obj->fw_addr_offset + offset) & pvr_dev->fw_dev.fw_heap_info.offset_mask) | in pvr_mips_get_fw_addr_with_offset()