Lines Matching refs:WREG32_SMC
570 WREG32_SMC(config_regs->offset, data); in ci_program_pt_config_registers()
860 WREG32_SMC(CG_THERMAL_INT, tmp); in ci_thermal_set_temperature_range()
867 WREG32_SMC(CG_THERMAL_CTRL, tmp); in ci_thermal_set_temperature_range()
884 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
893 WREG32_SMC(CG_THERMAL_INT, thermal_int); in ci_thermal_enable_alert()
920 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
924 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1098 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
1175 WREG32_SMC(CG_TACH_CTRL, tmp);
1191 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
1195 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_default_mode()
1215 WREG32_SMC(CG_TACH_CTRL, tmp); in ci_thermal_initialize()
1220 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_thermal_initialize()
1379 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_set_dpm_event_sources()
1383 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_set_dpm_event_sources()
1457 WREG32_SMC(LCAC_MC0_CNTL, 0x05); in ci_enable_sclk_mclk_dpm()
1458 WREG32_SMC(LCAC_MC1_CNTL, 0x05); in ci_enable_sclk_mclk_dpm()
1459 WREG32_SMC(LCAC_CPL_CNTL, 0x100005); in ci_enable_sclk_mclk_dpm()
1463 WREG32_SMC(LCAC_MC0_CNTL, 0x400005); in ci_enable_sclk_mclk_dpm()
1464 WREG32_SMC(LCAC_MC1_CNTL, 0x400005); in ci_enable_sclk_mclk_dpm()
1465 WREG32_SMC(LCAC_CPL_CNTL, 0x500005); in ci_enable_sclk_mclk_dpm()
1493 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_start_dpm()
1497 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_start_dpm()
1554 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_stop_dpm()
1558 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_stop_dpm()
1585 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_enable_sclk_control()
1871 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_enable_thermal_protection()
1880 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_enable_acpi_power_management()
1957 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); in ci_program_display_gap()
1968 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp); in ci_program_display_gap()
1986 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_enable_spread_spectrum()
1991 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp); in ci_enable_spread_spectrum()
1995 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_enable_spread_spectrum()
2001 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); in ci_program_sstp()
2012 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp); in ci_enable_display_gap()
2021 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_program_vc()
2023 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0); in ci_program_vc()
2024 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1); in ci_program_vc()
2025 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2); in ci_program_vc()
2026 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3); in ci_program_vc()
2027 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4); in ci_program_vc()
2028 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5); in ci_program_vc()
2029 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6); in ci_program_vc()
2030 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7); in ci_program_vc()
2039 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp); in ci_clear_vc()
2041 WREG32_SMC(CG_FTV_0, 0); in ci_clear_vc()
2042 WREG32_SMC(CG_FTV_1, 0); in ci_clear_vc()
2043 WREG32_SMC(CG_FTV_2, 0); in ci_clear_vc()
2044 WREG32_SMC(CG_FTV_3, 0); in ci_clear_vc()
2045 WREG32_SMC(CG_FTV_4, 0); in ci_clear_vc()
2046 WREG32_SMC(CG_FTV_5, 0); in ci_clear_vc()
2047 WREG32_SMC(CG_FTV_6, 0); in ci_clear_vc()
2048 WREG32_SMC(CG_FTV_7, 0); in ci_clear_vc()
2060 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1); in ci_upload_firmware()
3541 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); in ci_init_smc_table()
4049 WREG32_SMC(DPM_TABLE_475, tmp); in ci_update_uvd_dpm()
4087 WREG32_SMC(DPM_TABLE_475, tmp); in ci_update_vce_dpm()
4117 WREG32_SMC(DPM_TABLE_475, tmp);
4750 WREG32_SMC(GENERAL_PWRMGT, tmp); in ci_enable_voltage_control()
5840 WREG32_SMC(CNB_PWRMGT_CNTL, tmp); in ci_dpm_init()