Lines Matching refs:src_offset
2805 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2870 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2871 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2874 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2876 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2895 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2896 src_offset <<= 8; in evergreen_dma_cs_parse()
2905 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2906 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2914 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2916 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2929 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2930 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2933 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2935 src_offset + count, radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2975 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2976 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2977 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2979 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3015 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3016 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3017 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3019 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3077 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3078 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3079 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3081 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3106 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3107 src_offset <<= 8; in evergreen_dma_cs_parse()
3116 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3117 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3125 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3127 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
3164 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3165 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3166 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
3168 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()