Lines Matching refs:ioaddr
78 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mac_err() argument
83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
84 writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS); in dwmac5_handle_mac_err()
126 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mtl_err() argument
131 value = readl(ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
132 writel(value, ioaddr + MTL_ECC_INT_STATUS); in dwmac5_handle_mtl_err()
174 void __iomem *ioaddr, bool correctable, in dwmac5_handle_dma_err() argument
179 value = readl(ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
180 writel(value, ioaddr + DMA_ECC_INT_STATUS); in dwmac5_handle_dma_err()
186 int dwmac5_safety_feat_config(void __iomem *ioaddr, unsigned int asp, in dwmac5_safety_feat_config() argument
209 value = readl(ioaddr + MTL_ECC_CONTROL); in dwmac5_safety_feat_config()
221 writel(value, ioaddr + MTL_ECC_CONTROL); in dwmac5_safety_feat_config()
224 value = readl(ioaddr + MTL_ECC_INT_ENABLE); in dwmac5_safety_feat_config()
229 writel(value, ioaddr + MTL_ECC_INT_ENABLE); in dwmac5_safety_feat_config()
232 value = readl(ioaddr + DMA_ECC_INT_ENABLE); in dwmac5_safety_feat_config()
234 writel(value, ioaddr + DMA_ECC_INT_ENABLE); in dwmac5_safety_feat_config()
241 value = readl(ioaddr + MAC_FSM_CONTROL); in dwmac5_safety_feat_config()
246 writel(value, ioaddr + MAC_FSM_CONTROL); in dwmac5_safety_feat_config()
249 value = readl(ioaddr + MTL_DPP_CONTROL); in dwmac5_safety_feat_config()
252 writel(value, ioaddr + MTL_DPP_CONTROL); in dwmac5_safety_feat_config()
263 writel(value, ioaddr + MTL_DPP_CONTROL); in dwmac5_safety_feat_config()
268 void __iomem *ioaddr, unsigned int asp, in dwmac5_safety_feat_irq_status() argument
278 mtl = readl(ioaddr + MTL_SAFETY_INT_STATUS); in dwmac5_safety_feat_irq_status()
279 dma = readl(ioaddr + DMA_SAFETY_INT_STATUS); in dwmac5_safety_feat_irq_status()
284 dwmac5_handle_mac_err(ndev, ioaddr, corr, stats); in dwmac5_safety_feat_irq_status()
291 dwmac5_handle_mtl_err(ndev, ioaddr, corr, stats); in dwmac5_safety_feat_irq_status()
298 dwmac5_handle_dma_err(ndev, ioaddr, corr, stats); in dwmac5_safety_feat_irq_status()
330 static int dwmac5_rxp_disable(void __iomem *ioaddr) in dwmac5_rxp_disable() argument
334 val = readl(ioaddr + MTL_OPERATION_MODE); in dwmac5_rxp_disable()
336 writel(val, ioaddr + MTL_OPERATION_MODE); in dwmac5_rxp_disable()
338 return readl_poll_timeout(ioaddr + MTL_RXP_CONTROL_STATUS, val, in dwmac5_rxp_disable()
342 static void dwmac5_rxp_enable(void __iomem *ioaddr) in dwmac5_rxp_enable() argument
346 val = readl(ioaddr + MTL_OPERATION_MODE); in dwmac5_rxp_enable()
348 writel(val, ioaddr + MTL_OPERATION_MODE); in dwmac5_rxp_enable()
351 static int dwmac5_rxp_update_single_entry(void __iomem *ioaddr, in dwmac5_rxp_update_single_entry() argument
362 ret = readl_poll_timeout(ioaddr + MTL_RXP_IACC_CTRL_STATUS, in dwmac5_rxp_update_single_entry()
369 writel(val, ioaddr + MTL_RXP_IACC_DATA); in dwmac5_rxp_update_single_entry()
373 writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS); in dwmac5_rxp_update_single_entry()
377 writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS); in dwmac5_rxp_update_single_entry()
381 writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS); in dwmac5_rxp_update_single_entry()
384 ret = readl_poll_timeout(ioaddr + MTL_RXP_IACC_CTRL_STATUS, in dwmac5_rxp_update_single_entry()
433 int dwmac5_rxp_config(void __iomem *ioaddr, struct stmmac_tc_entry *entries, in dwmac5_rxp_config() argument
442 old_val = readl(ioaddr + GMAC_CONFIG); in dwmac5_rxp_config()
444 writel(val, ioaddr + GMAC_CONFIG); in dwmac5_rxp_config()
447 ret = dwmac5_rxp_disable(ioaddr); in dwmac5_rxp_config()
474 ret = dwmac5_rxp_update_single_entry(ioaddr, entry, nve); in dwmac5_rxp_config()
482 ret = dwmac5_rxp_update_single_entry(ioaddr, frag, nve); in dwmac5_rxp_config()
499 ret = dwmac5_rxp_update_single_entry(ioaddr, entry, nve); in dwmac5_rxp_config()
509 writel(val, ioaddr + MTL_RXP_CONTROL_STATUS); in dwmac5_rxp_config()
512 dwmac5_rxp_enable(ioaddr); in dwmac5_rxp_config()
516 writel(old_val, ioaddr + GMAC_CONFIG); in dwmac5_rxp_config()
520 int dwmac5_flex_pps_config(void __iomem *ioaddr, int index, in dwmac5_flex_pps_config() argument
524 u32 tnsec = readl(ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index)); in dwmac5_flex_pps_config()
525 u32 val = readl(ioaddr + MAC_PPS_CONTROL); in dwmac5_flex_pps_config()
540 writel(val, ioaddr + MAC_PPS_CONTROL); in dwmac5_flex_pps_config()
546 writel(val, ioaddr + MAC_PPS_CONTROL); in dwmac5_flex_pps_config()
548 writel(cfg->start.tv_sec, ioaddr + MAC_PPSx_TARGET_TIME_SEC(index)); in dwmac5_flex_pps_config()
552 writel(cfg->start.tv_nsec, ioaddr + MAC_PPSx_TARGET_TIME_NSEC(index)); in dwmac5_flex_pps_config()
562 writel(period - 1, ioaddr + MAC_PPSx_INTERVAL(index)); in dwmac5_flex_pps_config()
568 writel(period - 1, ioaddr + MAC_PPSx_WIDTH(index)); in dwmac5_flex_pps_config()
572 writel(val, ioaddr + MAC_PPS_CONTROL); in dwmac5_flex_pps_config()
576 void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, in dwmac5_fpe_configure() argument
584 value = readl(ioaddr + GMAC_RXQ_CTRL1); in dwmac5_fpe_configure()
587 writel(value, ioaddr + GMAC_RXQ_CTRL1); in dwmac5_fpe_configure()
591 writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS); in dwmac5_fpe_configure()
593 value = readl(ioaddr + GMAC_INT_EN); in dwmac5_fpe_configure()
598 readl(ioaddr + MAC_FPE_CTRL_STS); in dwmac5_fpe_configure()
606 writel(value, ioaddr + GMAC_INT_EN); in dwmac5_fpe_configure()
609 int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *dev) in dwmac5_fpe_irq_status() argument
619 value = readl(ioaddr + MAC_FPE_CTRL_STS); in dwmac5_fpe_irq_status()
644 void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe_cfg *cfg, in dwmac5_fpe_send_mpacket() argument
654 writel(value, ioaddr + MAC_FPE_CTRL_STS); in dwmac5_fpe_send_mpacket()
657 int dwmac5_fpe_get_add_frag_size(const void __iomem *ioaddr) in dwmac5_fpe_get_add_frag_size() argument
659 return FIELD_GET(DWMAC5_ADD_FRAG_SZ, readl(ioaddr + MTL_FPE_CTRL_STS)); in dwmac5_fpe_get_add_frag_size()
662 void dwmac5_fpe_set_add_frag_size(void __iomem *ioaddr, u32 add_frag_size) in dwmac5_fpe_set_add_frag_size() argument
666 value = readl(ioaddr + MTL_FPE_CTRL_STS); in dwmac5_fpe_set_add_frag_size()
668 ioaddr + MTL_FPE_CTRL_STS); in dwmac5_fpe_set_add_frag_size()
719 val = readl(priv->ioaddr + MTL_FPE_CTRL_STS); in dwmac5_fpe_map_preemption_class()
721 priv->ioaddr + MTL_FPE_CTRL_STS); in dwmac5_fpe_map_preemption_class()