Lines Matching refs:parf
266 void __iomem *parf; /* DT parf */ member
355 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_base()
357 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_base()
372 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
374 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
378 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
380 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + in qcom_pcie_configure_dbi_atu_base()
384 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); in qcom_pcie_configure_dbi_atu_base()
385 writel(SLV_ADDR_SPACE_SZ, pcie->parf + in qcom_pcie_configure_dbi_atu_base()
445 writel(1, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_deinit_2_1_0()
490 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
492 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
503 pcie->parf + PARF_PCS_DEEMPH); in qcom_pcie_post_init_2_1_0()
506 pcie->parf + PARF_PCS_SWING); in qcom_pcie_post_init_2_1_0()
507 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); in qcom_pcie_post_init_2_1_0()
512 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
515 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_1_0()
519 val = readl(pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
524 writel(val, pcie->parf + PARF_PHY_REFCLK); in qcom_pcie_post_init_2_1_0()
609 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
612 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); in qcom_pcie_post_init_1_0_0()
625 val = readl(pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
627 writel(val, pcie->parf + PARF_LTSSM); in qcom_pcie_2_3_2_ltssm_enable()
689 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
691 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_2()
696 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
698 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_2()
700 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
702 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_3_2()
704 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
706 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_post_init_2_3_2()
875 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
877 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_3_3()
884 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_3_3()
885 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_3_3()
968 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_init_2_7_0()
971 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
973 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_init_2_7_0()
978 val = readl(pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
980 writel(val, pcie->parf + PARF_SYS_CTRL); in qcom_pcie_init_2_7_0()
982 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
984 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_init_2_7_0()
987 val = readl(pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
989 writel(val, pcie->parf + PARF_PM_CTRL); in qcom_pcie_init_2_7_0()
991 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
993 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); in qcom_pcie_init_2_7_0()
1010 pcie->parf + PARF_NO_SNOOP_OVERIDE); in qcom_pcie_post_init_2_7_0()
1055 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; in qcom_pcie_config_sid_1_9_0()
1067 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1069 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); in qcom_pcie_config_sid_1_9_0()
1184 val = readl(pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1186 writel(val, pcie->parf + PARF_PHY_CTRL); in qcom_pcie_post_init_2_9_0()
1190 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); in qcom_pcie_post_init_2_9_0()
1192 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); in qcom_pcie_post_init_2_9_0()
1200 pcie->parf + PARF_SYS_CTRL); in qcom_pcie_post_init_2_9_0()
1202 writel(0, pcie->parf + PARF_Q2A_FLUSH); in qcom_pcie_post_init_2_9_0()
1218 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); in qcom_pcie_post_init_2_9_0()
1551 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); in qcom_pcie_global_irq_thread()
1553 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); in qcom_pcie_global_irq_thread()
1615 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); in qcom_pcie_probe()
1616 if (IS_ERR(pcie->parf)) { in qcom_pcie_probe()
1617 ret = PTR_ERR(pcie->parf); in qcom_pcie_probe()
1719 writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); in qcom_pcie_probe()