Lines Matching refs:dev_err
75 dev_err(dev, "missing core reset property in node\n"); in rockchip_pcie_parse_dt()
82 dev_err(dev, "missing mgmt reset property in node\n"); in rockchip_pcie_parse_dt()
90 dev_err(dev, "missing mgmt-sticky reset property in node\n"); in rockchip_pcie_parse_dt()
97 dev_err(dev, "missing pipe reset property in node\n"); in rockchip_pcie_parse_dt()
104 dev_err(dev, "missing pm reset property in node\n"); in rockchip_pcie_parse_dt()
111 dev_err(dev, "missing pclk reset property in node\n"); in rockchip_pcie_parse_dt()
118 dev_err(dev, "missing aclk reset property in node\n"); in rockchip_pcie_parse_dt()
132 dev_err(dev, "aclk clock not found\n"); in rockchip_pcie_parse_dt()
138 dev_err(dev, "aclk_perf clock not found\n"); in rockchip_pcie_parse_dt()
144 dev_err(dev, "hclk clock not found\n"); in rockchip_pcie_parse_dt()
150 dev_err(dev, "pm clock not found\n"); in rockchip_pcie_parse_dt()
172 dev_err(dev, "assert aclk_rst err %d\n", err); in rockchip_pcie_init_port()
178 dev_err(dev, "assert pclk_rst err %d\n", err); in rockchip_pcie_init_port()
184 dev_err(dev, "assert pm_rst err %d\n", err); in rockchip_pcie_init_port()
191 dev_err(dev, "init phy%d err %d\n", i, err); in rockchip_pcie_init_port()
198 dev_err(dev, "assert core_rst err %d\n", err); in rockchip_pcie_init_port()
204 dev_err(dev, "assert mgmt_rst err %d\n", err); in rockchip_pcie_init_port()
210 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err); in rockchip_pcie_init_port()
216 dev_err(dev, "assert pipe_rst err %d\n", err); in rockchip_pcie_init_port()
224 dev_err(dev, "deassert pm_rst err %d\n", err); in rockchip_pcie_init_port()
230 dev_err(dev, "deassert aclk_rst err %d\n", err); in rockchip_pcie_init_port()
236 dev_err(dev, "deassert pclk_rst err %d\n", err); in rockchip_pcie_init_port()
260 dev_err(dev, "power on phy%d err %d\n", i, err); in rockchip_pcie_init_port()
271 dev_err(dev, "PHY PLLs could not lock, %d\n", err); in rockchip_pcie_init_port()
281 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err); in rockchip_pcie_init_port()
287 dev_err(dev, "deassert core_rst err %d\n", err); in rockchip_pcie_init_port()
293 dev_err(dev, "deassert mgmt_rst err %d\n", err); in rockchip_pcie_init_port()
299 dev_err(dev, "deassert pipe_rst err %d\n", err); in rockchip_pcie_init_port()
345 dev_err(dev, "missing phy for lane %d: %ld\n", in rockchip_pcie_get_phys()
377 dev_err(dev, "unable to enable aclk_pcie clock\n"); in rockchip_pcie_enable_clocks()
383 dev_err(dev, "unable to enable aclk_perf_pcie clock\n"); in rockchip_pcie_enable_clocks()
389 dev_err(dev, "unable to enable hclk_pcie clock\n"); in rockchip_pcie_enable_clocks()
395 dev_err(dev, "unable to enable clk_pcie_pm clock\n"); in rockchip_pcie_enable_clocks()