Lines Matching refs:inf
91 struct hw_pmu_info *inf; member
140 struct hw_pmu_info inf; member
723 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); in xgene_pmu_read_counter32()
748 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx)); in xgene_pmu_write_counter32()
767 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx)); in xgene_pmu_write_evttype()
773 writel(val, pmu_dev->inf->csr + PMU_PMAMR0); in xgene_pmu_write_agentmsk()
782 writel(val, pmu_dev->inf->csr + PMU_PMAMR1); in xgene_pmu_write_agent1msk()
793 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET); in xgene_pmu_enable_counter()
795 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET); in xgene_pmu_enable_counter()
803 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR); in xgene_pmu_disable_counter()
805 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR); in xgene_pmu_disable_counter()
813 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET); in xgene_pmu_enable_counter_int()
815 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET); in xgene_pmu_enable_counter_int()
823 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR); in xgene_pmu_disable_counter_int()
825 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR); in xgene_pmu_disable_counter_int()
832 val = readl(pmu_dev->inf->csr + PMU_PMCR); in xgene_pmu_reset_counters()
834 writel(val, pmu_dev->inf->csr + PMU_PMCR); in xgene_pmu_reset_counters()
841 val = readl(pmu_dev->inf->csr + PMU_PMCR); in xgene_pmu_start_counters()
843 writel(val, pmu_dev->inf->csr + PMU_PMCR); in xgene_pmu_start_counters()
850 val = readl(pmu_dev->inf->csr + PMU_PMCR); in xgene_pmu_stop_counters()
852 writel(val, pmu_dev->inf->csr + PMU_PMCR); in xgene_pmu_stop_counters()
941 if (pmu_dev->inf->type == PMU_TYPE_IOB) in xgene_perf_enable_event()
1127 pmu->inf = &ctx->inf; in xgene_pmu_dev_add()
1130 switch (pmu->inf->type) { in xgene_pmu_dev_add()
1132 if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask)) in xgene_pmu_dev_add()
1150 if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask)) in xgene_pmu_dev_add()
1158 if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask)) in xgene_pmu_dev_add()
1182 void __iomem *csr = pmu_dev->inf->csr; in _xgene_pmu_isr()
1450 struct hw_pmu_info *inf; in acpi_get_pmu_hw_inf() local
1501 inf = &ctx->inf; in acpi_get_pmu_hw_inf()
1502 inf->type = type; in acpi_get_pmu_hw_inf()
1503 inf->csr = dev_csr; in acpi_get_pmu_hw_inf()
1504 inf->enable_mask = 1 << enable_bit; in acpi_get_pmu_hw_inf()
1564 switch (ctx->inf.type) { in acpi_pmu_dev_add()
1618 struct hw_pmu_info *inf; in fdt_get_pmu_hw_inf() local
1648 inf = &ctx->inf; in fdt_get_pmu_hw_inf()
1649 inf->type = type; in fdt_get_pmu_hw_inf()
1650 inf->csr = dev_csr; in fdt_get_pmu_hw_inf()
1651 inf->enable_mask = 1 << enable_bit; in fdt_get_pmu_hw_inf()
1686 switch (ctx->inf.type) { in fdt_pmu_probe_pmu_dev()