Lines Matching refs:com
300 void __iomem *com; member
386 void __iomem *com = u2_banks->com; in u2_phy_params_show() local
398 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_params_show()
404 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_params_show()
419 tmp = readl(com + U3P_USBPHYACR1); in u2_phy_params_show()
425 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_params_show()
431 tmp = readl(com + U3P_USBPHYACR6); in u2_phy_params_show()
458 void __iomem *com = u2_banks->com; in u2_phy_params_write() local
473 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val); in u2_phy_params_write()
477 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val); in u2_phy_params_write()
487 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val); in u2_phy_params_write()
491 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val); in u2_phy_params_write()
495 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val); in u2_phy_params_write()
704 void __iomem *com = u2_banks->com; in hs_slew_rate_calibrate() local
718 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); in hs_slew_rate_calibrate()
762 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, in hs_slew_rate_calibrate()
766 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); in hs_slew_rate_calibrate()
822 void __iomem *com = u2_banks->com; in u2_phy_pll_26m_set() local
827 mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0); in u2_phy_pll_26m_set()
829 mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3); in u2_phy_pll_26m_set()
831 writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV); in u2_phy_pll_26m_set()
833 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1, in u2_phy_pll_26m_set()
841 void __iomem *com = u2_banks->com; in u2_phy_instance_init() local
845 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); in u2_phy_instance_init()
847 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, in u2_phy_instance_init()
850 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN); in u2_phy_instance_init()
852 mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); in u2_phy_instance_init()
855 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); in u2_phy_instance_init()
857 mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); in u2_phy_instance_init()
861 mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN); in u2_phy_instance_init()
863 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_init()
865 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_init()
867 mtk_phy_set_bits(com + U3P_U2PHYDTM0, in u2_phy_instance_init()
873 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); in u2_phy_instance_init()
875 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); in u2_phy_instance_init()
887 void __iomem *com = u2_banks->com; in u2_phy_instance_power_on() local
891 mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); in u2_phy_instance_power_on()
893 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); in u2_phy_instance_power_on()
895 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); in u2_phy_instance_power_on()
898 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_power_on()
900 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); in u2_phy_instance_power_on()
909 void __iomem *com = u2_banks->com; in u2_phy_instance_power_off() local
913 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); in u2_phy_instance_power_off()
915 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); in u2_phy_instance_power_off()
917 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); in u2_phy_instance_power_off()
920 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); in u2_phy_instance_power_off()
922 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_power_off()
932 void __iomem *com = u2_banks->com; in u2_phy_instance_exit() local
936 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); in u2_phy_instance_exit()
938 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM); in u2_phy_instance_exit()
949 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
964 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
1097 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; in phy_v1_banks_init()
1125 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; in phy_v2_banks_init()
1175 void __iomem *com = u2_banks->com; in u2_phy_props_set() local
1178 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN); in u2_phy_props_set()
1181 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, in u2_phy_props_set()
1185 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, in u2_phy_props_set()
1189 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, in u2_phy_props_set()
1197 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, in u2_phy_props_set()
1202 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, in u2_phy_props_set()
1206 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, in u2_phy_props_set()
1356 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, in phy_efuse_set()