Lines Matching refs:regval
203 u32 regval; in pci1xxxx_acquire_sys_lock() local
205 return readx_poll_timeout(pci1xxxx_set_sys_lock, par, regval, in pci1xxxx_acquire_sys_lock()
206 (regval & SPI_SYSLOCK), 100, in pci1xxxx_acquire_sys_lock()
219 u32 regval; in pci1xxxx_check_spi_can_dma() local
232 regval = readl(spi_bus->reg_base + DEV_REV_REG); in pci1xxxx_check_spi_can_dma()
233 spi_bus->dev_rev = regval & DEV_REV_MASK; in pci1xxxx_check_spi_can_dma()
235 regval = readl(spi_bus->reg_base + in pci1xxxx_check_spi_can_dma()
237 pf_num = regval & SPI_PERI_ENBLE_PF_MASK; in pci1xxxx_check_spi_can_dma()
307 u32 regval; in pci1xxxx_spi_set_cs() local
310 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_set_cs()
312 regval |= SPI_FORCE_CE; in pci1xxxx_spi_set_cs()
313 regval &= ~SPI_MST_CTL_DEVSEL_MASK; in pci1xxxx_spi_set_cs()
314 regval |= (spi_get_chipselect(spi, 0) << 25); in pci1xxxx_spi_set_cs()
316 regval &= ~SPI_FORCE_CE; in pci1xxxx_spi_set_cs()
318 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_set_cs()
387 u32 regval; in pci1xxxx_spi_setup() local
389 regval = readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_spi_setup()
390 regval &= ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK | in pci1xxxx_spi_setup()
394 regval |= SPI_MST_CTL_MODE_SEL; in pci1xxxx_spi_setup()
396 regval |= FIELD_PREP(SPI_MST_CTL_CMD_LEN_MASK, len); in pci1xxxx_spi_setup()
397 regval |= FIELD_PREP(SPI_MST_CTL_SPEED_MASK, clkdiv); in pci1xxxx_spi_setup()
398 writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_spi_setup()
403 u32 regval; in pci1xxxx_start_spi_xfer() local
405 regval = readl(p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_start_spi_xfer()
406 regval |= SPI_MST_CTL_GO; in pci1xxxx_start_spi_xfer()
407 writel(regval, p->parent->reg_base + SPI_MST_CTL_REG_OFFSET(hw_inst)); in pci1xxxx_start_spi_xfer()
421 u32 regval; in pci1xxxx_spi_transfer_with_io() local
430 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_io()
431 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_io()
480 u32 regval; in pci1xxxx_spi_transfer_with_dma() local
486 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
487 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
498 regval = readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
499 writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_transfer_with_dma()
525 SPI_DMA_GLOBAL_RD_ENGINE_EN, regval, in pci1xxxx_spi_transfer_with_dma()
526 (regval == 0x0), 0, USEC_PER_MSEC); in pci1xxxx_spi_transfer_with_dma()
546 SPI_DMA_GLOBAL_WR_ENGINE_EN, regval, in pci1xxxx_spi_transfer_with_dma()
547 (regval == 0x0), 0, USEC_PER_MSEC); in pci1xxxx_spi_transfer_with_dma()
581 u32 regval; in pci1xxxx_spi_isr_io() local
584 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_io()
585 if (regval & SPI_INTR) { in pci1xxxx_spi_isr_io()
594 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_io()
632 u32 regval; in pci1xxxx_spi_isr_dma() local
636 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_RD_STS); in pci1xxxx_spi_isr_dma()
637 if (regval & SPI_DMA_DONE_INT_MASK) { in pci1xxxx_spi_isr_dma()
638 if (regval & SPI_DMA_CH0_DONE_INT) in pci1xxxx_spi_isr_dma()
640 if (regval & SPI_DMA_CH1_DONE_INT) in pci1xxxx_spi_isr_dma()
644 if (regval & SPI_DMA_ABORT_INT_MASK) { in pci1xxxx_spi_isr_dma()
648 writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_RD_CLR); in pci1xxxx_spi_isr_dma()
651 regval = readl(p->parent->dma_offset_bar + SPI_DMA_INTR_WR_STS); in pci1xxxx_spi_isr_dma()
652 if (regval & SPI_DMA_DONE_INT_MASK) { in pci1xxxx_spi_isr_dma()
653 if (regval & SPI_DMA_CH0_DONE_INT) in pci1xxxx_spi_isr_dma()
656 if (regval & SPI_DMA_CH1_DONE_INT) in pci1xxxx_spi_isr_dma()
661 if (regval & SPI_DMA_ABORT_INT_MASK) { in pci1xxxx_spi_isr_dma()
665 writel(regval, p->parent->dma_offset_bar + SPI_DMA_INTR_WR_CLR); in pci1xxxx_spi_isr_dma()
669 regval = readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_dma()
670 if (regval & SPI_INTR) { in pci1xxxx_spi_isr_dma()
674 writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); in pci1xxxx_spi_isr_dma()
705 u32 regval; in pci1xxxx_spi_probe() local
763 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe()
765 regval &= ~SPI_INTR; in pci1xxxx_spi_probe()
766 writel(regval, spi_bus->reg_base + in pci1xxxx_spi_probe()
785 regval = readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); in pci1xxxx_spi_probe()
787 regval |= (BIT(4)); in pci1xxxx_spi_probe()
789 regval &= ~(BIT(4)); in pci1xxxx_spi_probe()
791 writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); in pci1xxxx_spi_probe()
799 regval = readl(spi_bus->reg_base + in pci1xxxx_spi_probe()
801 regval &= ~SPI_INTR; in pci1xxxx_spi_probe()
802 writel(regval, spi_bus->reg_base + in pci1xxxx_spi_probe()
846 u32 regval; in store_restore_config() local
849 regval = readl(spi_ptr->reg_base + in store_restore_config()
851 regval &= SPI_MST_CTL_DEVSEL_MASK; in store_restore_config()
852 spi_sub_ptr->prev_val.dev_sel = (regval >> 25) & 7; in store_restore_config()
853 regval = readl(spi_ptr->reg_base + in store_restore_config()
855 regval &= SPI_MSI_VECTOR_SEL_MASK; in store_restore_config()
856 spi_sub_ptr->prev_val.msi_vector_sel = (regval >> 4) & 1; in store_restore_config()
858 regval = readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); in store_restore_config()
859 regval &= ~SPI_MST_CTL_DEVSEL_MASK; in store_restore_config()
860 regval |= (spi_sub_ptr->prev_val.dev_sel << 25); in store_restore_config()
861 writel(regval, in store_restore_config()
872 u32 regval = SPI_RESUME_CONFIG; in pci1xxxx_spi_resume() local
878 writel(regval, spi_ptr->reg_base + in pci1xxxx_spi_resume()