Lines Matching refs:dev_dbg
41 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
73 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_restore_global_registers()
158 dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__); in dwc2_restore_essential_regs()
272 dev_dbg(hsotg->dev, in dwc2_hib_restore_common()
276 dev_dbg(hsotg->dev, "restore done generated here\n"); in dwc2_hib_restore_common()
513 dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device"); in dwc2_force_mode()
562 dev_dbg(hsotg->dev, "Clearing force mode bits\n"); in dwc2_clear_force_mode()
609 dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n"); in dwc2_enable_acg()
629 dev_dbg(hsotg->dev, "Host Global Registers\n"); in dwc2_dump_host_registers()
631 dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
634 dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
637 dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
640 dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
643 dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
646 dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
650 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
655 dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
659 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); in dwc2_dump_host_registers()
661 dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
664 dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
667 dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
670 dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
673 dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
676 dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
680 dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", in dwc2_dump_host_registers()
701 dev_dbg(hsotg->dev, "Core Global Registers\n"); in dwc2_dump_global_registers()
703 dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
706 dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
709 dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
712 dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
715 dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
718 dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
721 dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
724 dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
727 dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
730 dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
733 dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
736 dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
739 dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
742 dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
745 dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
748 dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
751 dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
754 dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
757 dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
760 dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
763 dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
766 dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
769 dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
772 dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
776 dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", in dwc2_dump_global_registers()
976 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); in dwc2_init_fs_ls_pclk_sel()
1028 dev_dbg(hsotg->dev, "FS PHY selected\n"); in dwc2_fs_phy_init()
1050 dev_dbg(hsotg->dev, "Activating transceiver\n"); in dwc2_fs_phy_init()
1070 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); in dwc2_fs_phy_init()
1109 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n"); in dwc2_hs_phy_init()
1122 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n"); in dwc2_hs_phy_init()
1191 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); in dwc2_phy_init()