Lines Matching refs:regbase
356 u8 __iomem *regbase; member
396 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
397 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
402 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
411 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
413 caddr_t regbase,
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f; in cirrusfb_check_mclk()
639 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40; in cirrusfb_set_mclk_as_source()
645 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1; in cirrusfb_set_mclk_as_source()
649 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e); in cirrusfb_set_mclk_as_source()
651 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f); in cirrusfb_set_mclk_as_source()
663 u8 __iomem *regbase = cinfo->regbase; in cirrusfb_set_par_foo() local
749 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */ in cirrusfb_set_par_foo()
753 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal); in cirrusfb_set_par_foo()
756 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend); in cirrusfb_set_par_foo()
759 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8); in cirrusfb_set_par_foo()
763 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END, in cirrusfb_set_par_foo()
767 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart); in cirrusfb_set_par_foo()
773 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp); in cirrusfb_set_par_foo()
776 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff); in cirrusfb_set_par_foo()
794 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp); in cirrusfb_set_par_foo()
802 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp); in cirrusfb_set_par_foo()
805 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff); in cirrusfb_set_par_foo()
808 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32); in cirrusfb_set_par_foo()
811 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff); in cirrusfb_set_par_foo()
814 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff); in cirrusfb_set_par_foo()
817 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff); in cirrusfb_set_par_foo()
820 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff); in cirrusfb_set_par_foo()
835 vga_wcrt(regbase, CL_CRT1A, tmp); in cirrusfb_set_par_foo()
897 vga_wseq(regbase, CL_SEQRE, tmp); in cirrusfb_set_par_foo()
898 vga_wseq(regbase, CL_SEQR1E, nom); in cirrusfb_set_par_foo()
900 vga_wseq(regbase, CL_SEQRE, nom); in cirrusfb_set_par_foo()
901 vga_wseq(regbase, CL_SEQR1E, tmp); in cirrusfb_set_par_foo()
907 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7); in cirrusfb_set_par_foo()
911 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3); in cirrusfb_set_par_foo()
916 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2); in cirrusfb_set_par_foo()
918 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */ in cirrusfb_set_par_foo()
930 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0); in cirrusfb_set_par_foo()
932 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31); in cirrusfb_set_par_foo()
943 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */ in cirrusfb_set_par_foo()
954 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
961 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
962 vga_rseq(regbase, CL_SEQR7) & ~0x01); in cirrusfb_set_par_foo()
976 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
981 vga_wseq(regbase, CL_SEQRF, 0xd0); in cirrusfb_set_par_foo()
1007 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06); in cirrusfb_set_par_foo()
1009 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01); in cirrusfb_set_par_foo()
1028 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
1035 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
1036 vga_rseq(regbase, CL_SEQR7) | 0x01); in cirrusfb_set_par_foo()
1050 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1056 vga_wseq(regbase, CL_SEQRF, 0xb8); in cirrusfb_set_par_foo()
1072 vga_wgfx(regbase, VGA_GFX_MODE, 64); in cirrusfb_set_par_foo()
1092 vga_wseq(regbase, CL_SEQR7, 0x87); in cirrusfb_set_par_foo()
1094 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1098 vga_wseq(regbase, CL_SEQR7, 0x27); in cirrusfb_set_par_foo()
1100 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1107 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
1112 vga_wseq(regbase, CL_SEQR7, 0x17); in cirrusfb_set_par_foo()
1118 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
1119 vga_rseq(regbase, CL_SEQR7) & ~0x01); in cirrusfb_set_par_foo()
1131 vga_wgfx(regbase, VGA_GFX_MODE, 64); in cirrusfb_set_par_foo()
1151 vga_wseq(regbase, CL_SEQR7, 0x85); in cirrusfb_set_par_foo()
1153 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1157 vga_wseq(regbase, CL_SEQR7, 0x25); in cirrusfb_set_par_foo()
1159 vga_wseq(regbase, CL_SEQRF, 0xb0); in cirrusfb_set_par_foo()
1166 vga_wseq(regbase, CL_SEQR7, 0xa5); in cirrusfb_set_par_foo()
1170 vga_wseq(regbase, CL_SEQR7, 0x15); in cirrusfb_set_par_foo()
1176 vga_wseq(regbase, CL_SEQR7, in cirrusfb_set_par_foo()
1177 vga_rseq(regbase, CL_SEQR7) & ~0x01); in cirrusfb_set_par_foo()
1189 vga_wgfx(regbase, VGA_GFX_MODE, 64); in cirrusfb_set_par_foo()
1206 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff); in cirrusfb_set_par_foo()
1212 vga_wcrt(regbase, CL_CRT1B, tmp); in cirrusfb_set_par_foo()
1216 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1); in cirrusfb_set_par_foo()
1233 vga_wcrt(regbase, CL_CRT1E, tmp); in cirrusfb_set_par_foo()
1238 vga_wattr(regbase, CL_AR33, 0); in cirrusfb_set_par_foo()
1259 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp); in cirrusfb_set_par_foo()
1340 cirrusfb_WaitBLT(cinfo->regbase); in cirrusfb_pan_display()
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff); in cirrusfb_pan_display()
1344 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff); in cirrusfb_pan_display()
1347 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2; in cirrusfb_pan_display()
1356 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp); in cirrusfb_pan_display()
1360 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D); in cirrusfb_pan_display()
1365 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp); in cirrusfb_pan_display()
1373 vga_wattr(cinfo->regbase, CL_AR33, xpix); in cirrusfb_pan_display()
1412 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf; in cirrusfb_blank()
1413 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val); in cirrusfb_blank()
1434 vga_wgfx(cinfo->regbase, CL_GRE, val); in cirrusfb_blank()
1477 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00); in init_vgachip()
1480 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1484 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00); in init_vgachip()
1488 vga_wgfx(cinfo->regbase, CL_GR33, 0x00); in init_vgachip()
1517 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03); in init_vgachip()
1520 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21); in init_vgachip()
1525 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12); in init_vgachip()
1529 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98); in init_vgachip()
1537 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8); in init_vgachip()
1541 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f); in init_vgachip()
1542 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0); in init_vgachip()
1547 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff); in init_vgachip()
1549 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00); in init_vgachip()
1551 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a); in init_vgachip()
1555 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07); in init_vgachip()
1561 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00); in init_vgachip()
1563 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00); in init_vgachip()
1565 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00); in init_vgachip()
1567 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00); in init_vgachip()
1572 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00); in init_vgachip()
1574 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02); in init_vgachip()
1578 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00); in init_vgachip()
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20); in init_vgachip()
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00); in init_vgachip()
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00); in init_vgachip()
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00); in init_vgachip()
1589 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00); in init_vgachip()
1592 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02); in init_vgachip()
1595 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00); in init_vgachip()
1597 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00); in init_vgachip()
1599 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00); in init_vgachip()
1601 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00); in init_vgachip()
1603 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00); in init_vgachip()
1605 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00); in init_vgachip()
1607 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01); in init_vgachip()
1609 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f); in init_vgachip()
1611 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff); in init_vgachip()
1616 vga_wgfx(cinfo->regbase, CL_GRB, 0x20); in init_vgachip()
1621 vga_wgfx(cinfo->regbase, CL_GRB, 0x28); in init_vgachip()
1623 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */ in init_vgachip()
1624 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */ in init_vgachip()
1625 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */ in init_vgachip()
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00); in init_vgachip()
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01); in init_vgachip()
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02); in init_vgachip()
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03); in init_vgachip()
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04); in init_vgachip()
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05); in init_vgachip()
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06); in init_vgachip()
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07); in init_vgachip()
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08); in init_vgachip()
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09); in init_vgachip()
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a); in init_vgachip()
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b); in init_vgachip()
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c); in init_vgachip()
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d); in init_vgachip()
1645 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e); in init_vgachip()
1646 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f); in init_vgachip()
1649 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01); in init_vgachip()
1651 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00); in init_vgachip()
1653 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f); in init_vgachip()
1655 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00); in init_vgachip()
1660 vga_wgfx(cinfo->regbase, CL_GR31, 0x04); in init_vgachip()
1662 vga_wgfx(cinfo->regbase, CL_GR31, 0x00); in init_vgachip()
1725 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03) in cirrusfb_sync()
1762 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_fillrect()
1803 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel, in cirrusfb_copyarea()
1839 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1847 cirrusfb_RectFill(cinfo->regbase, in cirrusfb_imageblit()
1865 u8 __iomem *regbase) in cirrusfb_get_memsize() argument
1871 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14); in cirrusfb_get_memsize()
1875 unsigned char SRF = vga_rseq(regbase, CL_SEQRF); in cirrusfb_get_memsize()
1953 iounmap(cinfo->regbase); in cirrusfb_zorro_unmap()
2119 cinfo->regbase = NULL; in cirrusfb_pci_register()
2126 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase); in cirrusfb_pci_register()
2204 unsigned long regbase, ramsize, rambase; in cirrusfb_zorro_register() local
2213 regbase = zorro_resource_start(z) + zcl->regoffset; in cirrusfb_zorro_register()
2244 cirrusfb_board_info[btype].name, regbase, ramsize / MB_, in cirrusfb_zorro_register()
2256 info->fix.mmio_start = regbase; in cirrusfb_zorro_register()
2257 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024) in cirrusfb_zorro_register()
2258 : ZTWO_VADDR(regbase); in cirrusfb_zorro_register()
2259 if (!cinfo->regbase) { in cirrusfb_zorro_register()
2283 vga_wseq(cinfo->regbase, CL_SEQR1F, in cirrusfb_zorro_register()
2301 if (regbase > 16 * MB_) in cirrusfb_zorro_register()
2302 iounmap(cinfo->regbase); in cirrusfb_zorro_register()
2425 vga_w(cinfo->regbase, regofs + regnum, val); in WGen()
2441 return vga_r(cinfo->regbase, regofs + regnum); in RGen()
2449 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) { in AttrOn()
2452 vga_w(cinfo->regbase, VGA_ATT_IW, in AttrOn()
2453 vga_r(cinfo->regbase, VGA_ATT_R)); in AttrOn()
2457 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33); in AttrOn()
2460 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00); in AttrOn()
2512 assert(cinfo->regbase != NULL); in WSFR()
2514 z_writeb(val, cinfo->regbase + 0x8000); in WSFR()
2524 assert(cinfo->regbase != NULL); in WSFR2()
2526 z_writeb(val, cinfo->regbase + 0x9000); in WSFR2()
2537 vga_w(cinfo->regbase, VGA_PEL_IW, regnum); in WClut()
2545 vga_w(cinfo->regbase, data, red); in WClut()
2546 vga_w(cinfo->regbase, data, green); in WClut()
2547 vga_w(cinfo->regbase, data, blue); in WClut()
2549 vga_w(cinfo->regbase, data, blue); in WClut()
2550 vga_w(cinfo->regbase, data, green); in WClut()
2551 vga_w(cinfo->regbase, data, red); in WClut()
2562 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2568 *red = vga_r(cinfo->regbase, data);
2569 *green = vga_r(cinfo->regbase, data);
2570 *blue = vga_r(cinfo->regbase, data);
2572 *blue = vga_r(cinfo->regbase, data);
2573 *green = vga_r(cinfo->regbase, data);
2574 *red = vga_r(cinfo->regbase, data);
2586 static void cirrusfb_WaitBLT(u8 __iomem *regbase) in cirrusfb_WaitBLT() argument
2588 while (vga_rgfx(regbase, CL_GR31) & 0x08) in cirrusfb_WaitBLT()
2598 static void cirrusfb_set_blitter(u8 __iomem *regbase, in cirrusfb_set_blitter() argument
2606 vga_wgfx(regbase, CL_GR24, line_length & 0xff); in cirrusfb_set_blitter()
2608 vga_wgfx(regbase, CL_GR25, line_length >> 8); in cirrusfb_set_blitter()
2610 vga_wgfx(regbase, CL_GR26, line_length & 0xff); in cirrusfb_set_blitter()
2612 vga_wgfx(regbase, CL_GR27, line_length >> 8); in cirrusfb_set_blitter()
2616 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); in cirrusfb_set_blitter()
2618 vga_wgfx(regbase, CL_GR21, nwidth >> 8); in cirrusfb_set_blitter()
2622 vga_wgfx(regbase, CL_GR22, nheight & 0xff); in cirrusfb_set_blitter()
2624 vga_wgfx(regbase, CL_GR23, nheight >> 8); in cirrusfb_set_blitter()
2628 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff)); in cirrusfb_set_blitter()
2630 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8)); in cirrusfb_set_blitter()
2632 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16)); in cirrusfb_set_blitter()
2636 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff)); in cirrusfb_set_blitter()
2638 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8)); in cirrusfb_set_blitter()
2640 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16)); in cirrusfb_set_blitter()
2643 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */ in cirrusfb_set_blitter()
2646 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */ in cirrusfb_set_blitter()
2649 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */ in cirrusfb_set_blitter()
2658 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel, in cirrusfb_BitBLT() argument
2690 cirrusfb_WaitBLT(regbase); in cirrusfb_BitBLT()
2692 cirrusfb_set_blitter(regbase, nwidth, nheight, in cirrusfb_BitBLT()
2702 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel, in cirrusfb_RectFill() argument
2710 cirrusfb_WaitBLT(regbase); in cirrusfb_RectFill()
2714 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color); in cirrusfb_RectFill()
2715 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color); in cirrusfb_RectFill()
2719 vga_wgfx(regbase, CL_GR10, bg_color >> 8); in cirrusfb_RectFill()
2720 vga_wgfx(regbase, CL_GR11, fg_color >> 8); in cirrusfb_RectFill()
2724 vga_wgfx(regbase, CL_GR12, bg_color >> 16); in cirrusfb_RectFill()
2725 vga_wgfx(regbase, CL_GR13, fg_color >> 16); in cirrusfb_RectFill()
2729 vga_wgfx(regbase, CL_GR14, bg_color >> 24); in cirrusfb_RectFill()
2730 vga_wgfx(regbase, CL_GR15, fg_color >> 24); in cirrusfb_RectFill()
2733 cirrusfb_set_blitter(regbase, width - 1, height - 1, in cirrusfb_RectFill()
2818 caddr_t regbase, in cirrusfb_dbg_print_regs() argument
2834 val = vga_rcrt(regbase, (unsigned char) reg); in cirrusfb_dbg_print_regs()
2837 val = vga_rseq(regbase, (unsigned char) reg); in cirrusfb_dbg_print_regs()
2863 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase) in cirrusfb_dbg_reg_dump() argument
2867 cirrusfb_dbg_print_regs(info, regbase, CRT, in cirrusfb_dbg_reg_dump()
2921 cirrusfb_dbg_print_regs(info, regbase, SEQ, in cirrusfb_dbg_reg_dump()