Lines Matching refs:par
192 static u8 s3fb_ddc_read(struct s3fb_info *par) in s3fb_ddc_read() argument
194 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_read()
195 return readb(par->mmio + DDC_MMIO_REG); in s3fb_ddc_read()
197 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
200 static void s3fb_ddc_write(struct s3fb_info *par, u8 val) in s3fb_ddc_write() argument
202 if (s3fb_ddc_needs_mmio(par->chip)) in s3fb_ddc_write()
203 writeb(val, par->mmio + DDC_MMIO_REG); in s3fb_ddc_write()
205 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
210 struct s3fb_info *par = data; in s3fb_ddc_setscl() local
213 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setscl()
218 s3fb_ddc_write(par, reg); in s3fb_ddc_setscl()
223 struct s3fb_info *par = data; in s3fb_ddc_setsda() local
226 reg = s3fb_ddc_read(par) | DDC_DRIVE_EN; in s3fb_ddc_setsda()
231 s3fb_ddc_write(par, reg); in s3fb_ddc_setsda()
236 struct s3fb_info *par = data; in s3fb_ddc_getscl() local
238 return !!(s3fb_ddc_read(par) & DDC_SCL_IN); in s3fb_ddc_getscl()
243 struct s3fb_info *par = data; in s3fb_ddc_getsda() local
245 return !!(s3fb_ddc_read(par) & DDC_SDA_IN); in s3fb_ddc_getsda()
250 struct s3fb_info *par = info->par; in s3fb_setup_ddc_bus() local
252 strscpy(par->ddc_adapter.name, info->fix.id, in s3fb_setup_ddc_bus()
253 sizeof(par->ddc_adapter.name)); in s3fb_setup_ddc_bus()
254 par->ddc_adapter.owner = THIS_MODULE; in s3fb_setup_ddc_bus()
255 par->ddc_adapter.algo_data = &par->ddc_algo; in s3fb_setup_ddc_bus()
256 par->ddc_adapter.dev.parent = info->device; in s3fb_setup_ddc_bus()
257 par->ddc_algo.setsda = s3fb_ddc_setsda; in s3fb_setup_ddc_bus()
258 par->ddc_algo.setscl = s3fb_ddc_setscl; in s3fb_setup_ddc_bus()
259 par->ddc_algo.getsda = s3fb_ddc_getsda; in s3fb_setup_ddc_bus()
260 par->ddc_algo.getscl = s3fb_ddc_getscl; in s3fb_setup_ddc_bus()
261 par->ddc_algo.udelay = 10; in s3fb_setup_ddc_bus()
262 par->ddc_algo.timeout = 20; in s3fb_setup_ddc_bus()
263 par->ddc_algo.data = par; in s3fb_setup_ddc_bus()
265 i2c_set_adapdata(&par->ddc_adapter, par); in s3fb_setup_ddc_bus()
272 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_setup_ddc_bus()
273 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_setup_ddc_bus()
274 par->chip == CHIP_260_VIRGE_MX) in s3fb_setup_ddc_bus()
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
281 return i2c_bit_add_bus(&par->ddc_adapter); in s3fb_setup_ddc_bus()
314 struct s3fb_info *par = info->par; in s3fb_tilecursor() local
316 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
460 struct s3fb_info *par = info->par; in s3_set_pixclock() local
465 rv = svga_compute_pll((par->chip == CHIP_365_TRIO3D) ? &s3_trio3d_pll : &s3_pll, in s3_set_pixclock()
473 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
477 if (par->chip == CHIP_357_VIRGE_GX2 || in s3_set_pixclock()
478 par->chip == CHIP_359_VIRGE_GX2P || in s3_set_pixclock()
479 par->chip == CHIP_360_TRIO3D_1X || in s3_set_pixclock()
480 par->chip == CHIP_362_TRIO3D_2X || in s3_set_pixclock()
481 par->chip == CHIP_368_TRIO3D_2X || in s3_set_pixclock()
482 par->chip == CHIP_260_VIRGE_MX) { in s3_set_pixclock()
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
503 struct s3fb_info *par = info->par; in s3fb_open() local
505 mutex_lock(&(par->open_lock)); in s3fb_open()
506 if (par->ref_count == 0) { in s3fb_open()
507 void __iomem *vgabase = par->state.vgabase; in s3fb_open()
509 memset(&(par->state), 0, sizeof(struct vgastate)); in s3fb_open()
510 par->state.vgabase = vgabase; in s3fb_open()
511 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; in s3fb_open()
512 par->state.num_crtc = 0x70; in s3fb_open()
513 par->state.num_seq = 0x20; in s3fb_open()
514 save_vga(&(par->state)); in s3fb_open()
517 par->ref_count++; in s3fb_open()
518 mutex_unlock(&(par->open_lock)); in s3fb_open()
527 struct s3fb_info *par = info->par; in s3fb_release() local
529 mutex_lock(&(par->open_lock)); in s3fb_release()
530 if (par->ref_count == 0) { in s3fb_release()
531 mutex_unlock(&(par->open_lock)); in s3fb_release()
535 if (par->ref_count == 1) in s3fb_release()
536 restore_vga(&(par->state)); in s3fb_release()
538 par->ref_count--; in s3fb_release()
539 mutex_unlock(&(par->open_lock)); in s3fb_release()
548 struct s3fb_info *par = info->par; in s3fb_check_var() local
560 if ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)) in s3fb_check_var()
607 struct s3fb_info *par = info->par; in s3fb_set_par() local
652 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
653 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
654 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
655 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
658 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
659 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
662 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
663 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
664 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
665 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
666 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
667 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
670 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
671 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
675 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
676 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
678 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
688 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
690 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
691 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
692 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
693 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
694 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
695 par->chip != CHIP_260_VIRGE_MX) { in s3fb_set_par()
696 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
697 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
698 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
699 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
702 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
703 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
706 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
708 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
711 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
713 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
716 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
718 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
723 if (par->chip == CHIP_375_VIRGE_DX) { in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
725 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
729 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
730 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
731 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
733 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
734 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
737 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
738 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
739 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
740 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
741 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
742 par->chip == CHIP_365_TRIO3D || in s3fb_set_par()
743 par->chip == CHIP_375_VIRGE_DX || in s3fb_set_par()
744 par->chip == CHIP_385_VIRGE_GX || in s3fb_set_par()
745 par->chip == CHIP_260_VIRGE_MX) { in s3fb_set_par()
747 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
748 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
750 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
753 if (par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
754 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
755 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
756 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
757 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
758 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
759 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
761 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
763 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
771 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
774 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
775 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
778 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
782 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
787 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
800 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
801 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
804 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
808 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
810 par->chip == CHIP_357_VIRGE_GX2 || in s3fb_set_par()
811 par->chip == CHIP_359_VIRGE_GX2P || in s3fb_set_par()
812 par->chip == CHIP_360_TRIO3D_1X || in s3fb_set_par()
813 par->chip == CHIP_362_TRIO3D_2X || in s3fb_set_par()
814 par->chip == CHIP_368_TRIO3D_2X || in s3fb_set_par()
815 par->chip == CHIP_260_VIRGE_MX) in s3fb_set_par()
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
824 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
829 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
830 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
832 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
835 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
839 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
840 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
841 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
842 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
843 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
844 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
845 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
846 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
852 if (par->chip == CHIP_988_VIRGE_VX) { in s3fb_set_par()
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
857 } else if (par->chip == CHIP_365_TRIO3D) { in s3fb_set_par()
858 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
860 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
863 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
867 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
868 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
869 if (par->chip != CHIP_357_VIRGE_GX2 && in s3fb_set_par()
870 par->chip != CHIP_359_VIRGE_GX2P && in s3fb_set_par()
871 par->chip != CHIP_360_TRIO3D_1X && in s3fb_set_par()
872 par->chip != CHIP_362_TRIO3D_2X && in s3fb_set_par()
873 par->chip != CHIP_368_TRIO3D_2X && in s3fb_set_par()
874 par->chip != CHIP_260_VIRGE_MX) in s3fb_set_par()
881 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
885 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
886 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
893 if (par->chip != CHIP_988_VIRGE_VX) { in s3fb_set_par()
894 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
895 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
899 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
907 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
913 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
919 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
920 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
990 struct s3fb_info *par = info->par; in s3fb_blank() local
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1010 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
1011 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1015 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1016 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1028 struct s3fb_info *par = info->par; in s3fb_pan_display() local
1043 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1071 static int s3_identification(struct s3fb_info *par) in s3_identification() argument
1073 int chip = par->chip; in s3_identification()
1076 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1077 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1078 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1093 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1102 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1111 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1132 struct s3fb_info *par; in s3_pci_probe() local
1152 par = info->par; in s3_pci_probe()
1153 mutex_init(&par->open_lock); in s3_pci_probe()
1190 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1193 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1194 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1195 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1196 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1197 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1200 par->chip = id->driver_data & CHIP_MASK; in s3_pci_probe()
1201 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1202 if (par->chip & CHIP_UNDECIDED_FLAG) in s3_pci_probe()
1203 par->chip = s3_identification(par); in s3_pci_probe()
1207 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1208 if (par->chip == CHIP_360_TRIO3D_1X || in s3_pci_probe()
1209 par->chip == CHIP_362_TRIO3D_2X || in s3_pci_probe()
1210 par->chip == CHIP_368_TRIO3D_2X || in s3_pci_probe()
1211 par->chip == CHIP_365_TRIO3D) { in s3_pci_probe()
1223 } else if (par->chip == CHIP_357_VIRGE_GX2 || in s3_pci_probe()
1224 par->chip == CHIP_359_VIRGE_GX2P || in s3_pci_probe()
1225 par->chip == CHIP_260_VIRGE_MX) { in s3_pci_probe()
1234 } else if (par->chip == CHIP_988_VIRGE_VX) { in s3_pci_probe()
1250 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1264 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1265 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1266 par->mclk_freq = par->mclk_freq >> (regval >> 5); in s3_pci_probe()
1269 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1270 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1272 strcpy(info->fix.id, s3_names [par->chip]); in s3_pci_probe()
1279 info->pseudo_palette = (void*) (par->pseudo_palette); in s3_pci_probe()
1284 if (s3fb_ddc_needs_mmio(par->chip)) { in s3_pci_probe()
1285 par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE); in s3_pci_probe()
1286 if (par->mmio) in s3_pci_probe()
1287 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1292 if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio) in s3_pci_probe()
1294 u8 *edid = fb_ddc_read(&par->ddc_adapter); in s3_pci_probe()
1295 par->ddc_registered = true; in s3_pci_probe()
1361 info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000); in s3_pci_probe()
1363 if (par->chip == CHIP_UNKNOWN) in s3_pci_probe()
1365 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1366 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1367 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1368 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()
1374 par->wc_cookie = arch_phys_wc_add(info->fix.smem_start, in s3_pci_probe()
1385 if (par->ddc_registered) in s3_pci_probe()
1386 i2c_del_adapter(&par->ddc_adapter); in s3_pci_probe()
1387 if (par->mmio) in s3_pci_probe()
1388 iounmap(par->mmio); in s3_pci_probe()
1406 struct s3fb_info __maybe_unused *par; in s3_pci_remove() local
1409 par = info->par; in s3_pci_remove()
1410 arch_phys_wc_del(par->wc_cookie); in s3_pci_remove()
1415 if (par->ddc_registered) in s3_pci_remove()
1416 i2c_del_adapter(&par->ddc_adapter); in s3_pci_remove()
1417 if (par->mmio) in s3_pci_remove()
1418 iounmap(par->mmio); in s3_pci_remove()
1434 struct s3fb_info *par = info->par; in s3_pci_suspend() local
1439 mutex_lock(&(par->open_lock)); in s3_pci_suspend()
1441 if (par->ref_count == 0) { in s3_pci_suspend()
1442 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1449 mutex_unlock(&(par->open_lock)); in s3_pci_suspend()
1461 struct s3fb_info *par = info->par; in s3_pci_resume() local
1466 mutex_lock(&(par->open_lock)); in s3_pci_resume()
1468 if (par->ref_count == 0) { in s3_pci_resume()
1469 mutex_unlock(&(par->open_lock)); in s3_pci_resume()
1477 mutex_unlock(&(par->open_lock)); in s3_pci_resume()