Lines Matching refs:vgabase
197 return vga_rcrt(par->state.vgabase, DDC_REG); in s3fb_ddc_read()
205 vga_wcrt(par->state.vgabase, DDC_REG, val); in s3fb_ddc_write()
275 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); in s3fb_setup_ddc_bus()
277 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); in s3fb_setup_ddc_bus()
279 svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03); in s3fb_setup_ddc_bus()
316 svga_tilecursor(par->state.vgabase, info, cursor); in s3fb_tilecursor()
473 regval = vga_r(par->state.vgabase, VGA_MIS_R); in s3_set_pixclock()
474 vga_w(par->state.vgabase, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); in s3_set_pixclock()
483 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ in s3_set_pixclock()
484 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ in s3_set_pixclock()
486 vga_wseq(par->state.vgabase, 0x12, (n - 2) | (r << 5)); in s3_set_pixclock()
487 vga_wseq(par->state.vgabase, 0x13, m - 2); in s3_set_pixclock()
492 regval = vga_rseq (par->state.vgabase, 0x15); /* | 0x80; */ in s3_set_pixclock()
493 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
494 vga_wseq(par->state.vgabase, 0x15, regval | (1<<5)); in s3_set_pixclock()
495 vga_wseq(par->state.vgabase, 0x15, regval & ~(1<<5)); in s3_set_pixclock()
507 void __iomem *vgabase = par->state.vgabase; in s3fb_open() local
510 par->state.vgabase = vgabase; in s3fb_open()
652 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3fb_set_par()
653 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3fb_set_par()
654 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3fb_set_par()
655 svga_wcrt_mask(par->state.vgabase, 0x11, 0x00, 0x80); in s3fb_set_par()
658 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_set_par()
659 svga_wcrt_mask(par->state.vgabase, 0x17, 0x00, 0x80); in s3fb_set_par()
662 svga_set_default_gfx_regs(par->state.vgabase); in s3fb_set_par()
663 svga_set_default_atc_regs(par->state.vgabase); in s3fb_set_par()
664 svga_set_default_seq_regs(par->state.vgabase); in s3fb_set_par()
665 svga_set_default_crt_regs(par->state.vgabase); in s3fb_set_par()
666 svga_wcrt_multi(par->state.vgabase, s3_line_compare_regs, 0xFFFFFFFF); in s3fb_set_par()
667 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, 0); in s3fb_set_par()
670 svga_wcrt_mask(par->state.vgabase, 0x58, 0x10, 0x10); /* enable linear framebuffer */ in s3fb_set_par()
671 …svga_wcrt_mask(par->state.vgabase, 0x31, 0x08, 0x08); /* enable sequencer access to framebuffer ab… in s3fb_set_par()
675 svga_wcrt_mask(par->state.vgabase, 0x33, 0x00, 0x08); /* no DDR ? */ in s3fb_set_par()
676 svga_wcrt_mask(par->state.vgabase, 0x43, 0x00, 0x01); /* no DDR ? */ in s3fb_set_par()
678 svga_wcrt_mask(par->state.vgabase, 0x5D, 0x00, 0x28); /* Clear strange HSlen bits */ in s3fb_set_par()
688 svga_wcrt_multi(par->state.vgabase, s3_offset_regs, offset_value); in s3fb_set_par()
696 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ in s3fb_set_par()
697 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ in s3fb_set_par()
698 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ in s3fb_set_par()
699 vga_wcrt(par->state.vgabase, 0x62, 0xff); /* L parameter */ in s3fb_set_par()
702 vga_wcrt(par->state.vgabase, 0x3A, 0x35); in s3fb_set_par()
703 svga_wattr(par->state.vgabase, 0x33, 0x00); in s3fb_set_par()
706 svga_wcrt_mask(par->state.vgabase, 0x09, 0x80, 0x80); in s3fb_set_par()
708 svga_wcrt_mask(par->state.vgabase, 0x09, 0x00, 0x80); in s3fb_set_par()
711 svga_wcrt_mask(par->state.vgabase, 0x42, 0x20, 0x20); in s3fb_set_par()
713 svga_wcrt_mask(par->state.vgabase, 0x42, 0x00, 0x20); in s3fb_set_par()
716 svga_wcrt_mask(par->state.vgabase, 0x45, 0x00, 0x01); in s3fb_set_par()
718 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0x0C); in s3fb_set_par()
724 vga_wcrt(par->state.vgabase, 0x86, 0x80); in s3fb_set_par()
725 vga_wcrt(par->state.vgabase, 0x90, 0x00); in s3fb_set_par()
730 vga_wcrt(par->state.vgabase, 0x50, 0x00); in s3fb_set_par()
731 vga_wcrt(par->state.vgabase, 0x67, 0x50); in s3fb_set_par()
733 vga_wcrt(par->state.vgabase, 0x63, (mode <= 2) ? 0x90 : 0x09); in s3fb_set_par()
734 vga_wcrt(par->state.vgabase, 0x66, 0x90); in s3fb_set_par()
747 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); in s3fb_set_par()
748 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); in s3fb_set_par()
750 vga_wcrt(par->state.vgabase, 0x66, 0x81); in s3fb_set_par()
759 vga_wcrt(par->state.vgabase, 0x34, 0x00); in s3fb_set_par()
761 vga_wcrt(par->state.vgabase, 0x34, 0x10); in s3fb_set_par()
763 svga_wcrt_mask(par->state.vgabase, 0x31, 0x00, 0x40); in s3fb_set_par()
771 svga_set_textmode_vga_regs(par->state.vgabase); in s3fb_set_par()
774 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
775 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
778 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
782 svga_wcrt_mask(par->state.vgabase, 0x31, 0x40, 0x40); in s3fb_set_par()
787 vga_wgfx(par->state.vgabase, VGA_GFX_MODE, 0x40); in s3fb_set_par()
790 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
791 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
794 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
800 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
801 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
804 svga_wcrt_mask(par->state.vgabase, 0x3A, 0x00, 0x30); in s3fb_set_par()
808 svga_wcrt_mask(par->state.vgabase, 0x50, 0x00, 0x30); in s3fb_set_par()
816 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); in s3fb_set_par()
818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); in s3fb_set_par()
826 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
828 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
830 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
832 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
835 svga_wcrt_mask(par->state.vgabase, 0x67, 0x20, 0xF0); in s3fb_set_par()
839 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
840 svga_wcrt_mask(par->state.vgabase, 0x67, 0x30, 0xF0); in s3fb_set_par()
854 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
856 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
858 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
860 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
863 svga_wcrt_mask(par->state.vgabase, 0x67, 0x40, 0xF0); in s3fb_set_par()
867 svga_wcrt_mask(par->state.vgabase, 0x50, 0x10, 0x30); in s3fb_set_par()
868 svga_wcrt_mask(par->state.vgabase, 0x67, 0x50, 0xF0); in s3fb_set_par()
881 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
885 svga_wcrt_mask(par->state.vgabase, 0x50, 0x30, 0x30); in s3fb_set_par()
886 svga_wcrt_mask(par->state.vgabase, 0x67, 0xD0, 0xF0); in s3fb_set_par()
894 svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10); in s3fb_set_par()
895 svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80); in s3fb_set_par()
899 svga_set_timings(par->state.vgabase, &s3_timing_regs, &(info->var), hmul, 1, in s3fb_set_par()
907 vga_wcrt(par->state.vgabase, 0x3C, (htotal + 1) / 2); in s3fb_set_par()
913 svga_wcrt_multi(par->state.vgabase, s3_dtpc_regs, value); in s3fb_set_par()
919 svga_wcrt_mask(par->state.vgabase, 0x17, 0x80, 0x80); in s3fb_set_par()
920 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_set_par()
995 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
996 svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20); in s3fb_blank()
1000 svga_wcrt_mask(par->state.vgabase, 0x56, 0x00, 0x06); in s3fb_blank()
1001 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1005 svga_wcrt_mask(par->state.vgabase, 0x56, 0x02, 0x06); in s3fb_blank()
1006 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1010 svga_wcrt_mask(par->state.vgabase, 0x56, 0x04, 0x06); in s3fb_blank()
1011 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1015 svga_wcrt_mask(par->state.vgabase, 0x56, 0x06, 0x06); in s3fb_blank()
1016 svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20); in s3fb_blank()
1043 svga_wcrt_multi(par->state.vgabase, s3_start_address_regs, offset); in s3fb_pan_display()
1076 u8 cr30 = vga_rcrt(par->state.vgabase, 0x30); in s3_identification()
1077 u8 cr2e = vga_rcrt(par->state.vgabase, 0x2e); in s3_identification()
1078 u8 cr2f = vga_rcrt(par->state.vgabase, 0x2f); in s3_identification()
1093 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1102 u8 cr6f = vga_rcrt(par->state.vgabase, 0x6f); in s3_identification()
1111 switch (vga_rcrt(par->state.vgabase, 0x2f)) { in s3_identification()
1190 par->state.vgabase = (void __iomem *) (unsigned long) vga_res.start; in s3_pci_probe()
1193 cr38 = vga_rcrt(par->state.vgabase, 0x38); in s3_pci_probe()
1194 cr39 = vga_rcrt(par->state.vgabase, 0x39); in s3_pci_probe()
1195 vga_wseq(par->state.vgabase, 0x08, 0x06); in s3_pci_probe()
1196 vga_wcrt(par->state.vgabase, 0x38, 0x48); in s3_pci_probe()
1197 vga_wcrt(par->state.vgabase, 0x39, 0xA5); in s3_pci_probe()
1201 par->rev = vga_rcrt(par->state.vgabase, 0x2f); in s3_pci_probe()
1207 regval = vga_rcrt(par->state.vgabase, 0x36); in s3_pci_probe()
1250 regval = vga_rcrt(par->state.vgabase, 0x37); in s3_pci_probe()
1264 regval = vga_rseq(par->state.vgabase, 0x10); in s3_pci_probe()
1265 par->mclk_freq = ((vga_rseq(par->state.vgabase, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2); in s3_pci_probe()
1269 vga_wcrt(par->state.vgabase, 0x38, cr38); in s3_pci_probe()
1270 vga_wcrt(par->state.vgabase, 0x39, cr39); in s3_pci_probe()
1287 svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */ in s3_pci_probe()
1365 vga_rcrt(par->state.vgabase, 0x2d), in s3_pci_probe()
1366 vga_rcrt(par->state.vgabase, 0x2e), in s3_pci_probe()
1367 vga_rcrt(par->state.vgabase, 0x2f), in s3_pci_probe()
1368 vga_rcrt(par->state.vgabase, 0x30)); in s3_pci_probe()