Lines Matching refs:__u32
51 __u32 major_version; /* from KFD */
52 __u32 minor_version; /* from KFD */
71 __u32 ring_size; /* to KFD */
72 __u32 gpu_id; /* to KFD */
73 __u32 queue_type; /* to KFD */
74 __u32 queue_percentage; /* to KFD */
75 __u32 queue_priority; /* to KFD */
76 __u32 queue_id; /* from KFD */
81 __u32 ctx_save_restore_size; /* to KFD */
82 __u32 ctl_stack_size; /* to KFD */
83 __u32 sdma_engine_id; /* to KFD */
84 __u32 pad;
88 __u32 queue_id; /* to KFD */
89 __u32 pad;
95 __u32 queue_id; /* to KFD */
96 __u32 ring_size; /* to KFD */
97 __u32 queue_percentage; /* to KFD */
98 __u32 queue_priority; /* to KFD */
102 __u32 queue_id; /* to KFD */
103 __u32 num_cu_mask; /* to KFD */
109 __u32 ctl_stack_used_size; /* from KFD */
110 __u32 save_area_used_size; /* from KFD */
111 __u32 queue_id; /* to KFD */
112 __u32 pad;
117 __u32 gpu_id; /* to KFD */
118 __u32 pad;
129 __u32 gpu_id;
130 __u32 location_id;
131 __u32 vendor_id;
132 __u32 device_id;
133 __u32 revision_id;
134 __u32 subsystem_vendor_id;
135 __u32 subsystem_device_id;
136 __u32 fw_version;
137 __u32 gfx_target_version;
138 __u32 simd_count;
139 __u32 max_waves_per_simd;
140 __u32 array_count;
141 __u32 simd_arrays_per_engine;
142 __u32 num_xcc;
143 __u32 capability;
144 __u32 debug_prop;
155 __u32 gpu_id; /* to KFD */
156 __u32 default_policy; /* to KFD */
157 __u32 alternate_policy; /* to KFD */
158 __u32 pad;
174 __u32 gpu_id; /* to KFD */
175 __u32 pad;
185 __u32 gpu_id; /* from KFD */
186 __u32 pad;
200 __u32 num_of_nodes;
201 __u32 pad;
213 __u32 num_of_nodes;
214 __u32 pad;
222 __u32 gpu_id; /* to KFD */
223 __u32 pad;
227 __u32 gpu_id; /* to KFD */
228 __u32 pad;
233 __u32 gpu_id; /* to KFD */
234 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
239 __u32 gpu_id; /* to KFD */
240 __u32 buf_size_in_bytes; /*including gpu_id and buf_size */
278 __u32 event_trigger_data; /* from KFD - signal events only */
279 __u32 event_type; /* to KFD */
280 __u32 auto_reset; /* to KFD */
281 __u32 node_id; /* to KFD - only valid for certain
283 __u32 event_id; /* from KFD */
284 __u32 event_slot_index; /* from KFD */
288 __u32 event_id; /* to KFD */
289 __u32 pad;
293 __u32 event_id; /* to KFD */
294 __u32 pad;
298 __u32 event_id; /* to KFD */
299 __u32 pad;
303 __u32 NotPresent; /* Page not present or supervisor privilege */
304 __u32 ReadOnly; /* Write access to a read-only page */
305 __u32 NoExecute; /* Execute access to a page marked NX */
306 __u32 imprecise; /* Can't determine the exact fault address */
313 __u32 gpu_id;
314 __u32 ErrorType; /* 0 = no RAS error,
324 __u32 reset_type;
325 __u32 reset_cause;
326 __u32 memory_lost;
327 __u32 gpu_id;
346 __u32 event_id; /* to KFD */
347 __u32 pad;
353 __u32 num_events; /* to KFD */
354 __u32 wait_for_all; /* to KFD */
355 __u32 timeout; /* to KFD */
356 __u32 wait_result; /* from KFD */
361 __u32 gpu_id; /* to KFD */
362 __u32 pad;
373 __u32 num_tile_configs;
377 __u32 num_macro_tile_configs;
379 __u32 gpu_id; /* to KFD */
380 __u32 gb_addr_config; /* from KFD */
381 __u32 num_banks; /* from KFD */
382 __u32 num_ranks; /* from KFD */
391 __u32 gpu_id; /* to KFD */
392 __u32 pad;
396 __u32 drm_fd; /* to KFD */
397 __u32 gpu_id; /* to KFD */
434 __u32 gpu_id; /* to KFD */
435 __u32 flags;
464 __u32 n_devices; /* to KFD */
465 __u32 n_success; /* to/from KFD */
475 __u32 n_devices; /* to KFD */
476 __u32 n_success; /* to/from KFD */
487 __u32 queue_id; /* to KFD */
488 __u32 num_gws; /* to KFD */
489 __u32 first_gws; /* from KFD */
490 __u32 pad;
496 __u32 metadata_size; /* to KFD (space allocated by user)
499 __u32 gpu_id; /* from KFD */
500 __u32 flags; /* from KFD (KFD_IOC_ALLOC_MEM_FLAGS) */
501 __u32 dmabuf_fd; /* to KFD */
507 __u32 gpu_id; /* to KFD */
508 __u32 dmabuf_fd; /* to KFD */
513 __u32 flags; /* to KFD */
514 __u32 dmabuf_fd; /* from KFD */
572 __u32 gpuid; /* to KFD */
573 __u32 anon_fd; /* from KFD */
695 __u32 num_devices; /* Used during ops: PROCESS_INFO, RESTORE */
696 __u32 num_bos; /* Used during ops: PROCESS_INFO, RESTORE */
697 __u32 num_objects; /* Used during ops: PROCESS_INFO, RESTORE */
698 __u32 pid; /* Used during ops: PROCESS_INFO, RESUME */
699 __u32 op;
703 __u32 user_gpu_id;
704 __u32 actual_gpu_id;
705 __u32 drm_fd;
706 __u32 pad;
714 __u32 gpu_id; /* This is the user_gpu_id */
715 __u32 alloc_flags;
716 __u32 dmabuf_fd;
717 __u32 pad;
807 __u32 type;
808 __u32 value;
852 __u32 op;
853 __u32 nattr;
1029 __u32 runtime_state;
1030 __u32 ttmp_setup;
1058 __u32 mode_mask;
1059 __u32 capabilities_mask;
1069 __u32 queue_id;
1070 __u32 gpu_id;
1071 __u32 ring_size;
1072 __u32 queue_type;
1073 __u32 ctx_save_restore_area_size;
1074 __u32 reserved;
1086 __u32 control_stack_offset;
1087 __u32 control_stack_size;
1088 __u32 wave_state_offset;
1089 __u32 wave_state_size;
1091 __u32 debug_offset;
1092 __u32 debug_size;
1094 __u32 err_event_id;
1095 __u32 reserved1;
1166 __u32 rinfo_size;
1167 __u32 dbg_fd;
1191 __u32 gpu_id;
1192 __u32 queue_id;
1234 __u32 override_mode;
1235 __u32 enable_mask;
1236 __u32 support_request_mask;
1237 __u32 pad;
1252 __u32 launch_mode;
1253 __u32 pad;
1289 __u32 num_queues;
1290 __u32 grace_period;
1313 __u32 num_queues;
1314 __u32 pad;
1337 __u32 mode;
1338 __u32 mask;
1339 __u32 gpu_id;
1340 __u32 id;
1358 __u32 gpu_id;
1359 __u32 id;
1375 __u32 flags;
1376 __u32 pad;
1404 __u32 gpu_id;
1405 __u32 queue_id;
1431 __u32 info_size;
1432 __u32 source_id;
1433 __u32 exception_code;
1434 __u32 clear_exception;
1469 __u32 num_queues;
1470 __u32 entry_size;
1505 __u32 num_devices;
1506 __u32 entry_size;
1521 __u32 pid;
1522 __u32 op;