Lines Matching refs:snd_sof_dsp_write
83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); in init_dma_descriptor()
84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); in init_dma_descriptor()
97 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); in configure_dma_descriptor()
98 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); in configure_dma_descriptor()
99 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); in configure_dma_descriptor()
131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), in config_dma_channel()
146 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); in config_dma_channel()
147 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); in config_dma_channel()
148 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); in config_dma_channel()
149 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); in config_dma_channel()
150 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); in config_dma_channel()
282 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); in configure_and_run_sha_dma()
294 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); in configure_and_run_sha_dma()
296 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); in configure_and_run_sha_dma()
297 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); in configure_and_run_sha_dma()
298 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); in configure_and_run_sha_dma()
311 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); in configure_and_run_sha_dma()
382 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); in memcpy_to_scratch()
416 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); in acp_irq_thread()
433 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, in acp_irq_handler()
441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); in acp_irq_handler()
448 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); in acp_irq_handler()
449 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); in acp_irq_handler()
452 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); in acp_irq_handler()
453 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); in acp_irq_handler()
461 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, in acp_irq_handler()
508 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, in acp_power_on()
525 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); in acp_reset()
535 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); in acp_reset()
543 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); in acp_reset()
546 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); in acp_reset()
549 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); in acp_reset()
558 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); in acp_dsp_reset()
568 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); in acp_dsp_reset()
589 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); in acp_init()
632 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); in amd_sof_acp_suspend()