Lines Matching refs:irq
88 int irq; in gic_get_best_irq() local
94 for (irq = 0; irq < s->num_irq; irq++) { in gic_get_best_irq()
95 if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && in gic_get_best_irq()
96 (!GIC_DIST_TEST_ACTIVE(irq, cm)) && in gic_get_best_irq()
97 (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) { in gic_get_best_irq()
98 if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) { in gic_get_best_irq()
99 *best_prio = GIC_DIST_GET_PRIORITY(irq, cpu); in gic_get_best_irq()
100 *best_irq = irq; in gic_get_best_irq()
353 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, in gic_set_irq_11mpcore() argument
357 GIC_DIST_SET_LEVEL(irq, cm); in gic_set_irq_11mpcore()
358 if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) { in gic_set_irq_11mpcore()
359 DPRINTF("Set %d pending mask %x\n", irq, target); in gic_set_irq_11mpcore()
360 GIC_DIST_SET_PENDING(irq, target); in gic_set_irq_11mpcore()
363 GIC_DIST_CLEAR_LEVEL(irq, cm); in gic_set_irq_11mpcore()
367 static void gic_set_irq_generic(GICState *s, int irq, int level, in gic_set_irq_generic() argument
371 GIC_DIST_SET_LEVEL(irq, cm); in gic_set_irq_generic()
372 DPRINTF("Set %d pending mask %x\n", irq, target); in gic_set_irq_generic()
373 if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) { in gic_set_irq_generic()
374 GIC_DIST_SET_PENDING(irq, target); in gic_set_irq_generic()
377 GIC_DIST_CLEAR_LEVEL(irq, cm); in gic_set_irq_generic()
382 static void gic_set_irq(void *opaque, int irq, int level) in gic_set_irq() argument
392 if (irq < (s->num_irq - GIC_INTERNAL)) { in gic_set_irq()
395 irq += GIC_INTERNAL; in gic_set_irq()
396 target = GIC_DIST_TARGET(irq); in gic_set_irq()
399 irq -= (s->num_irq - GIC_INTERNAL); in gic_set_irq()
400 cpu = irq / GIC_INTERNAL; in gic_set_irq()
401 irq %= GIC_INTERNAL; in gic_set_irq()
406 assert(irq >= GIC_NR_SGIS); in gic_set_irq()
408 if (level == GIC_DIST_TEST_LEVEL(irq, cm)) { in gic_set_irq()
413 gic_set_irq_11mpcore(s, irq, level, cm, target); in gic_set_irq()
415 gic_set_irq_generic(s, irq, level, cm, target); in gic_set_irq()
417 trace_gic_set_irq(irq, level, cm, target); in gic_set_irq()
449 static int gic_get_group_priority(GICState *s, int cpu, int irq) in gic_get_group_priority() argument
460 gic_test_group(s, irq, cpu)) { in gic_get_group_priority()
473 return gic_get_priority(s, irq, cpu) & mask; in gic_get_group_priority()
476 static void gic_activate_irq(GICState *s, int cpu, int irq) in gic_activate_irq() argument
481 int prio = gic_get_group_priority(s, cpu, irq); in gic_activate_irq()
491 } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { in gic_activate_irq()
500 gic_set_active(s, irq, cpu); in gic_activate_irq()
571 static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) in gic_clear_pending_sgi() argument
581 assert(s->sgi_pending[irq][cpu] != 0); in gic_clear_pending_sgi()
582 src = ctz32(s->sgi_pending[irq][cpu]); in gic_clear_pending_sgi()
583 s->sgi_pending[irq][cpu] &= ~(1 << src); in gic_clear_pending_sgi()
584 if (s->sgi_pending[irq][cpu] == 0) { in gic_clear_pending_sgi()
585 gic_clear_pending(s, irq, cpu); in gic_clear_pending_sgi()
587 ret = irq | ((src & 0x7) << 10); in gic_clear_pending_sgi()
589 uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu); in gic_clear_pending_sgi()
592 gic_clear_pending(s, irq, cpu); in gic_clear_pending_sgi()
593 ret = irq | (src << 10); in gic_clear_pending_sgi()
601 int ret, irq; in gic_acknowledge_irq() local
607 irq = gic_get_current_pending_irq(s, cpu, attrs); in gic_acknowledge_irq()
609 gic_get_vcpu_real_id(cpu), irq); in gic_acknowledge_irq()
611 if (irq >= GIC_MAXIRQ) { in gic_acknowledge_irq()
612 DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); in gic_acknowledge_irq()
613 return irq; in gic_acknowledge_irq()
616 if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) { in gic_acknowledge_irq()
617 DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq); in gic_acknowledge_irq()
621 gic_activate_irq(s, cpu, irq); in gic_acknowledge_irq()
627 gic_clear_pending(s, irq, cpu); in gic_acknowledge_irq()
628 ret = irq; in gic_acknowledge_irq()
630 if (irq < GIC_NR_SGIS) { in gic_acknowledge_irq()
631 ret = gic_clear_pending_sgi(s, irq, cpu); in gic_acknowledge_irq()
633 gic_clear_pending(s, irq, cpu); in gic_acknowledge_irq()
634 ret = irq; in gic_acknowledge_irq()
643 DPRINTF("ACK %d\n", irq); in gic_acknowledge_irq()
664 void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, in gic_dist_set_priority() argument
668 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { in gic_dist_set_priority()
676 if (irq < GIC_INTERNAL) { in gic_dist_set_priority()
677 s->priority1[irq][cpu] = val; in gic_dist_set_priority()
679 s->priority2[(irq) - GIC_INTERNAL] = val; in gic_dist_set_priority()
683 static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, in gic_dist_get_priority() argument
686 uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu); in gic_dist_get_priority()
689 if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) { in gic_dist_get_priority()
809 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) in gic_deactivate_irq() argument
813 if (irq >= GIC_MAXIRQ || (!gic_is_vcpu(cpu) && irq >= s->num_irq)) { in gic_deactivate_irq()
833 if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) { in gic_deactivate_irq()
847 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); in gic_deactivate_irq()
850 DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); in gic_deactivate_irq()
854 gic_clear_active(s, irq, cpu); in gic_deactivate_irq()
857 static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) in gic_complete_irq() argument
862 DPRINTF("EOI %d\n", irq); in gic_complete_irq()
869 if (irq >= GIC_MAXIRQ) { in gic_complete_irq()
877 bool valid = gic_virq_is_valid(s, irq, cpu); in gic_complete_irq()
889 gic_clear_active(s, irq, cpu); in gic_complete_irq()
897 if (irq >= s->num_irq) { in gic_complete_irq()
915 if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm) in gic_complete_irq()
916 && GIC_DIST_TEST_LEVEL(irq, cm) in gic_complete_irq()
917 && (GIC_DIST_TARGET(irq) & cm) != 0) { in gic_complete_irq()
918 DPRINTF("Set %d pending mask %x\n", irq, cm); in gic_complete_irq()
919 GIC_DIST_SET_PENDING(irq, cm); in gic_complete_irq()
923 group = gic_has_groups(s) && gic_test_group(s, irq, cpu); in gic_complete_irq()
926 DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq); in gic_complete_irq()
939 gic_clear_active(s, irq, cpu); in gic_complete_irq()
948 int irq; in gic_dist_readb() local
996 irq = (offset - 0x080) * 8; in gic_dist_readb()
997 if (irq >= s->num_irq) { in gic_dist_readb()
1001 if (GIC_DIST_TEST_GROUP(irq + i, cm)) { in gic_dist_readb()
1012 irq = (offset - 0x100) * 8; in gic_dist_readb()
1014 irq = (offset - 0x180) * 8; in gic_dist_readb()
1015 if (irq >= s->num_irq) in gic_dist_readb()
1020 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_readb()
1024 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { in gic_dist_readb()
1031 irq = (offset - 0x200) * 8; in gic_dist_readb()
1033 irq = (offset - 0x280) * 8; in gic_dist_readb()
1034 if (irq >= s->num_irq) in gic_dist_readb()
1037 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; in gic_dist_readb()
1040 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_readb()
1044 if (gic_test_pending(s, irq + i, mask)) { in gic_dist_readb()
1051 irq = (offset - 0x300) * 8; in gic_dist_readb()
1053 irq = (offset - 0x380) * 8; in gic_dist_readb()
1058 if (irq >= s->num_irq) in gic_dist_readb()
1061 mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK; in gic_dist_readb()
1064 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_readb()
1068 if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) { in gic_dist_readb()
1074 irq = (offset - 0x400); in gic_dist_readb()
1075 if (irq >= s->num_irq) in gic_dist_readb()
1077 res = gic_dist_get_priority(s, cpu, irq, attrs); in gic_dist_readb()
1084 irq = (offset - 0x800); in gic_dist_readb()
1085 if (irq >= s->num_irq) { in gic_dist_readb()
1088 if (irq < 29 && s->revision == REV_11MPCORE) { in gic_dist_readb()
1090 } else if (irq < GIC_INTERNAL) { in gic_dist_readb()
1093 res = GIC_DIST_TARGET(irq); in gic_dist_readb()
1098 irq = (offset - 0xc00) * 4; in gic_dist_readb()
1099 if (irq >= s->num_irq) in gic_dist_readb()
1104 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_readb()
1108 if (GIC_DIST_TEST_MODEL(irq + i)) { in gic_dist_readb()
1111 if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { in gic_dist_readb()
1124 irq = (offset - 0xf10); in gic_dist_readb()
1126 irq = (offset - 0xf20); in gic_dist_readb()
1131 !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { in gic_dist_readb()
1134 res = s->sgi_pending[irq][cpu]; in gic_dist_readb()
1195 int irq; in gic_dist_writeb() local
1221 irq = (offset - 0x80) * 8; in gic_dist_writeb()
1222 if (irq >= s->num_irq) { in gic_dist_writeb()
1227 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; in gic_dist_writeb()
1230 GIC_DIST_SET_GROUP(irq + i, cm); in gic_dist_writeb()
1233 GIC_DIST_CLEAR_GROUP(irq + i, cm); in gic_dist_writeb()
1242 irq = (offset - 0x100) * 8; in gic_dist_writeb()
1243 if (irq >= s->num_irq) in gic_dist_writeb()
1245 if (irq < GIC_NR_SGIS) { in gic_dist_writeb()
1252 (irq < GIC_INTERNAL) ? (1 << cpu) in gic_dist_writeb()
1253 : GIC_DIST_TARGET(irq + i); in gic_dist_writeb()
1254 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; in gic_dist_writeb()
1257 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1261 if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) { in gic_dist_writeb()
1262 DPRINTF("Enabled IRQ %d\n", irq + i); in gic_dist_writeb()
1263 trace_gic_enable_irq(irq + i); in gic_dist_writeb()
1265 GIC_DIST_SET_ENABLED(irq + i, cm); in gic_dist_writeb()
1273 && GIC_DIST_TEST_LEVEL(irq + i, mask) in gic_dist_writeb()
1274 && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) { in gic_dist_writeb()
1275 DPRINTF("Set %d pending mask %x\n", irq + i, mask); in gic_dist_writeb()
1276 GIC_DIST_SET_PENDING(irq + i, mask); in gic_dist_writeb()
1282 irq = (offset - 0x180) * 8; in gic_dist_writeb()
1283 if (irq >= s->num_irq) in gic_dist_writeb()
1285 if (irq < GIC_NR_SGIS) { in gic_dist_writeb()
1291 int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK; in gic_dist_writeb()
1294 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1298 if (GIC_DIST_TEST_ENABLED(irq + i, cm)) { in gic_dist_writeb()
1299 DPRINTF("Disabled IRQ %d\n", irq + i); in gic_dist_writeb()
1300 trace_gic_disable_irq(irq + i); in gic_dist_writeb()
1302 GIC_DIST_CLEAR_ENABLED(irq + i, cm); in gic_dist_writeb()
1307 irq = (offset - 0x200) * 8; in gic_dist_writeb()
1308 if (irq >= s->num_irq) in gic_dist_writeb()
1310 if (irq < GIC_NR_SGIS) { in gic_dist_writeb()
1316 int mask = (irq < GIC_INTERNAL) ? (1 << cpu) in gic_dist_writeb()
1317 : GIC_DIST_TARGET(irq + i); in gic_dist_writeb()
1320 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1324 GIC_DIST_SET_PENDING(irq + i, mask); in gic_dist_writeb()
1329 irq = (offset - 0x280) * 8; in gic_dist_writeb()
1330 if (irq >= s->num_irq) in gic_dist_writeb()
1332 if (irq < GIC_NR_SGIS) { in gic_dist_writeb()
1338 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1346 GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); in gic_dist_writeb()
1355 irq = (offset - 0x300) * 8; in gic_dist_writeb()
1356 if (irq >= s->num_irq) { in gic_dist_writeb()
1361 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; in gic_dist_writeb()
1365 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1370 GIC_DIST_SET_ACTIVE(irq + i, cm); in gic_dist_writeb()
1379 irq = (offset - 0x380) * 8; in gic_dist_writeb()
1380 if (irq >= s->num_irq) { in gic_dist_writeb()
1385 int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; in gic_dist_writeb()
1389 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1394 GIC_DIST_CLEAR_ACTIVE(irq + i, cm); in gic_dist_writeb()
1399 irq = (offset - 0x400); in gic_dist_writeb()
1400 if (irq >= s->num_irq) in gic_dist_writeb()
1402 gic_dist_set_priority(s, cpu, irq, value, attrs); in gic_dist_writeb()
1408 irq = (offset - 0x800); in gic_dist_writeb()
1409 if (irq >= s->num_irq) { in gic_dist_writeb()
1412 if (irq < 29 && s->revision == REV_11MPCORE) { in gic_dist_writeb()
1414 } else if (irq < GIC_INTERNAL) { in gic_dist_writeb()
1417 s->irq_target[irq] = value & ALL_CPU_MASK; in gic_dist_writeb()
1418 if (irq >= GIC_INTERNAL && s->irq_state[irq].pending) { in gic_dist_writeb()
1423 s->irq_state[irq].pending = value & ALL_CPU_MASK; in gic_dist_writeb()
1428 irq = (offset - 0xc00) * 4; in gic_dist_writeb()
1429 if (irq >= s->num_irq) in gic_dist_writeb()
1431 if (irq < GIC_NR_SGIS) in gic_dist_writeb()
1435 !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { in gic_dist_writeb()
1441 GIC_DIST_SET_MODEL(irq + i); in gic_dist_writeb()
1443 GIC_DIST_CLEAR_MODEL(irq + i); in gic_dist_writeb()
1447 GIC_DIST_SET_EDGE_TRIGGER(irq + i); in gic_dist_writeb()
1449 GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i); in gic_dist_writeb()
1460 irq = (offset - 0xf10); in gic_dist_writeb()
1463 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { in gic_dist_writeb()
1464 s->sgi_pending[irq][cpu] &= ~value; in gic_dist_writeb()
1465 if (s->sgi_pending[irq][cpu] == 0) { in gic_dist_writeb()
1466 GIC_DIST_CLEAR_PENDING(irq, 1 << cpu); in gic_dist_writeb()
1474 irq = (offset - 0xf20); in gic_dist_writeb()
1477 GIC_DIST_TEST_GROUP(irq, 1 << cpu)) { in gic_dist_writeb()
1478 GIC_DIST_SET_PENDING(irq, 1 << cpu); in gic_dist_writeb()
1479 s->sgi_pending[irq][cpu] |= value; in gic_dist_writeb()
1504 int irq; in gic_dist_writel() local
1509 irq = value & 0xf; in gic_dist_writel()
1525 GIC_DIST_SET_PENDING(irq, mask); in gic_dist_writel()
1528 s->sgi_pending[irq][target_cpu] |= (1 << cpu); in gic_dist_writel()