Lines Matching refs:index
122 static inline void dwc2_update_hc_irq(DWC2State *s, int index) in dwc2_update_hc_irq() argument
124 uint32_t host_intr = 1 << (index >> 3); in dwc2_update_hc_irq()
126 if (s->hreg1[index + 2] & s->hreg1[index + 3]) { in dwc2_update_hc_irq()
224 USBEndpoint *ep, uint32_t index, bool send) in dwc2_handle_packet() argument
227 uint32_t hcchar = s->hreg1[index]; in dwc2_handle_packet()
228 uint32_t hctsiz = s->hreg1[index + 4]; in dwc2_handle_packet()
229 uint32_t hcdma = s->hreg1[index + 5]; in dwc2_handle_packet()
247 chan = index >> 3; in dwc2_handle_packet()
315 p->index = index; in dwc2_handle_packet()
350 s->hreg1[index + 4] = hctsiz; in dwc2_handle_packet()
352 s->hreg1[index + 5] = hcdma; in dwc2_handle_packet()
367 s->hreg1[index + 2] |= intr; in dwc2_handle_packet()
379 s->hreg1[index] = hcchar; in dwc2_handle_packet()
384 s->hreg1[index + 2] |= intr; in dwc2_handle_packet()
387 dwc2_update_hc_irq(s, index); in dwc2_handle_packet()
396 p->index = index; in dwc2_handle_packet()
402 dwc2_update_hc_irq(s, index); in dwc2_handle_packet()
418 assert(port->index == 0); in dwc2_attach()
469 assert(port->index == 0); in dwc2_detach()
482 assert(port->index == 0); in dwc2_child_detach()
490 assert(port->index == 0); in dwc2_wakeup()
507 assert(port->index == 0); in dwc2_async_packet_complete()
511 trace_usb_dwc2_async_packet_complete(port, packet, p->index >> 3, dev, in dwc2_async_packet_complete()
521 dwc2_handle_packet(s, p->devadr, dev, ep, p->index, false); in dwc2_async_packet_complete()
592 dwc2_handle_packet(s, p->devadr, dev, ep, p->index, true); in dwc2_work_bh()
611 static void dwc2_enable_chan(DWC2State *s, uint32_t index) in dwc2_enable_chan() argument
620 assert((index >> 3) < DWC2_NB_CHAN); in dwc2_enable_chan()
621 p = &s->packet[index >> 3]; in dwc2_enable_chan()
622 hcchar = s->hreg1[index]; in dwc2_enable_chan()
623 hctsiz = s->hreg1[index + 4]; in dwc2_enable_chan()
633 trace_usb_dwc2_enable_chan(index >> 3, dev, &p->packet, epnum); in dwc2_enable_chan()
658 dwc2_handle_packet(s, devadr, dev, ep, index, true); in dwc2_enable_chan()
671 static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, int index, in dwc2_glbreg_read() argument
683 val = s->glbreg[index]; in dwc2_glbreg_read()
690 s->glbreg[index] = val; in dwc2_glbreg_read()
696 trace_usb_dwc2_glbreg_read(addr, glbregnm[index], val); in dwc2_glbreg_read()
700 static void dwc2_glbreg_write(void *ptr, hwaddr addr, int index, uint64_t val, in dwc2_glbreg_write() argument
715 mmio = &s->glbreg[index]; in dwc2_glbreg_write()
791 trace_usb_dwc2_glbreg_write(addr, glbregnm[index], orig, old, val); in dwc2_glbreg_write()
799 static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, int index, in dwc2_fszreg_read() argument
811 val = s->fszreg[index]; in dwc2_fszreg_read()
817 static void dwc2_fszreg_write(void *ptr, hwaddr addr, int index, uint64_t val, in dwc2_fszreg_write() argument
831 mmio = &s->fszreg[index]; in dwc2_fszreg_write()
845 static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, int index, in dwc2_hreg0_read() argument
857 val = s->hreg0[index]; in dwc2_hreg0_read()
868 trace_usb_dwc2_hreg0_read(addr, hreg0nm[index], val); in dwc2_hreg0_read()
872 static void dwc2_hreg0_write(void *ptr, hwaddr addr, int index, uint64_t val, in dwc2_hreg0_write() argument
889 mmio = &s->hreg0[index]; in dwc2_hreg0_write()
943 trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, in dwc2_hreg0_write()
949 trace_usb_dwc2_hreg0_write(addr, hreg0nm[index], orig, old, val); in dwc2_hreg0_write()
968 static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, int index, in dwc2_hreg1_read() argument
980 val = s->hreg1[index]; in dwc2_hreg1_read()
982 trace_usb_dwc2_hreg1_read(addr, hreg1nm[index & 7], addr >> 5, val); in dwc2_hreg1_read()
986 static void dwc2_hreg1_write(void *ptr, hwaddr addr, int index, uint64_t val, in dwc2_hreg1_write() argument
1003 mmio = &s->hreg1[index]; in dwc2_hreg1_write()
1040 trace_usb_dwc2_hreg1_write(addr, hreg1nm[index & 7], index >> 3, orig, in dwc2_hreg1_write()
1046 s->hreg1[(index & ~7) + 2] |= HCINTMSK_CHHLTD; in dwc2_hreg1_write()
1051 dwc2_enable_chan(s, index & ~7); in dwc2_hreg1_write()
1055 dwc2_update_hc_irq(s, index & ~7); in dwc2_hreg1_write()
1063 static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, int index, in dwc2_pcgreg_read() argument
1075 val = s->pcgreg[index]; in dwc2_pcgreg_read()
1077 trace_usb_dwc2_pcgreg_read(addr, pcgregnm[index], val); in dwc2_pcgreg_read()
1081 static void dwc2_pcgreg_write(void *ptr, hwaddr addr, int index, in dwc2_pcgreg_write() argument
1095 mmio = &s->pcgreg[index]; in dwc2_pcgreg_write()
1098 trace_usb_dwc2_pcgreg_write(addr, pcgregnm[index], orig, old, val); in dwc2_pcgreg_write()
1405 VMSTATE_UINT32(index, DWC2Packet),