Lines Matching refs:idx
515 u32 idx; in apply_tamper_pin_list_config() local
519 for (idx = 0; idx < size; idx++) { in apply_tamper_pin_list_config()
520 debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad, in apply_tamper_pin_list_config()
521 confs[idx].mux_conf); in apply_tamper_pin_list_config()
522 pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); in apply_tamper_pin_list_config()
634 u32 idx = 0; in do_snvs_cfg() local
641 conf.hp.lock = hextoul(argv[++idx], NULL); in do_snvs_cfg()
642 conf.hp.secvio_ctl = hextoul(argv[++idx], NULL); in do_snvs_cfg()
643 conf.lp.lock = hextoul(argv[++idx], NULL); in do_snvs_cfg()
644 conf.lp.secvio_ctl = hextoul(argv[++idx], NULL); in do_snvs_cfg()
645 conf.lp.tamper_filt_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
646 conf.lp.tamper_det_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
647 conf.lp.tamper_det_cfg2 = hextoul(argv[++idx], NULL); in do_snvs_cfg()
648 conf.lp.tamper_filt1_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
649 conf.lp.tamper_filt2_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
650 conf.lp.act_tamper1_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
651 conf.lp.act_tamper2_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
652 conf.lp.act_tamper3_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
653 conf.lp.act_tamper4_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
654 conf.lp.act_tamper5_cfg = hextoul(argv[++idx], NULL); in do_snvs_cfg()
655 conf.lp.act_tamper_ctl = hextoul(argv[++idx], NULL); in do_snvs_cfg()
656 conf.lp.act_tamper_clk_ctl = hextoul(argv[++idx], NULL); in do_snvs_cfg()
657 conf.lp.act_tamper_routing_ctl1 = hextoul(argv[++idx], NULL); in do_snvs_cfg()
658 conf.lp.act_tamper_routing_ctl2 = hextoul(argv[++idx], NULL); in do_snvs_cfg()
686 u32 idx = 0; in do_snvs_dgo_cfg() local
693 conf.tamper_offset_ctl = hextoul(argv[++idx], NULL); in do_snvs_dgo_cfg()
694 conf.tamper_pull_ctl = hextoul(argv[++idx], NULL); in do_snvs_dgo_cfg()
695 conf.tamper_ana_test_ctl = hextoul(argv[++idx], NULL); in do_snvs_dgo_cfg()
696 conf.tamper_sensor_trim_ctl = hextoul(argv[++idx], NULL); in do_snvs_dgo_cfg()
697 conf.tamper_misc_ctl = hextoul(argv[++idx], NULL); in do_snvs_dgo_cfg()
698 conf.tamper_core_volt_mon_ctl = hextoul(argv[++idx], NULL); in do_snvs_dgo_cfg()
722 u32 idx = 0; in do_tamper_pin_cfg() local
729 conf.pad = dectoul(argv[++idx], NULL); in do_tamper_pin_cfg()
730 conf.mux_conf = hextoul(argv[++idx], NULL); in do_tamper_pin_cfg()
757 u32 idx = 0; in do_snvs_clear_status() local
764 conf.lp.status = hextoul(argv[++idx], NULL); in do_snvs_clear_status()
765 conf.lp.tamper_det_status = hextoul(argv[++idx], NULL); in do_snvs_clear_status()
797 u32 idx; in do_snvs_sec_status() local
864 for (idx = 0; idx < ARRAY_SIZE(pads); idx++) { in do_snvs_sec_status()
865 u8 pad_id = pads[idx]; in do_snvs_sec_status()
876 for (idx = 0; idx < ARRAY_SIZE(fuses); idx++) { in do_snvs_sec_status()
877 u32 fuse_id = fuses[idx]; in do_snvs_sec_status()
888 for (idx = 0; idx < ARRAY_SIZE(snvs); idx++) { in do_snvs_sec_status()
889 struct snvs_reg *reg = &snvs[idx]; in do_snvs_sec_status()
908 for (idx = 0; idx < ARRAY_SIZE(dgo); idx++) { in do_snvs_sec_status()
909 u8 dgo_id = dgo[idx]; in do_snvs_sec_status()