Lines Matching refs:regs
223 void __iomem *regs; in ddr_init() local
226 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in ddr_init()
230 writel(DDR_CTL_CONFIG_VAL, regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
234 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
238 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); in ddr_init()
240 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); in ddr_init()
244 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); in ddr_init()
248 writel(DDR1_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); in ddr_init()
250 writel(DDR1_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); in ddr_init()
252 writel(DDR1_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()
256 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
260 writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
264 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
268 writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
272 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
276 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
280 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
282 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
286 writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
290 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
294 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); in ddr_init()
298 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
301 writel(DDR1_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
303 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
305 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
308 regs + QCA953X_DDR_REG_CTL_CONF); in ddr_init()
312 writel(0xffff, regs + AR71XX_DDR_REG_RD_CYCLE); in ddr_init()
316 writel(DDR_BURST_VAL, regs + QCA953X_DDR_REG_BURST); in ddr_init()
318 writel(DDR_BURST2_VAL, regs + QCA953X_DDR_REG_BURST2); in ddr_init()
322 writel(0xfffff, regs + QCA953X_DDR_REG_TIMEOUT_MAX); in ddr_init()
326 writel(DDR2_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG); in ddr_init()
328 writel(DDR2_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2); in ddr_init()
330 writel(DDR2_CONF3_REG_VAL, regs + QCA953X_DDR_REG_CONFIG3); in ddr_init()
334 writel(DDR2_CONF_VAL, regs + QCA953X_DDR_REG_DDR2_CONFIG); in ddr_init()
338 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
342 writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
346 writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
350 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
354 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
358 writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
362 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
366 writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
370 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
372 writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
376 writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE); in ddr_init()
380 writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
384 writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
388 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
392 writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR); in ddr_init()
396 writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL); in ddr_init()
400 writel(DDR_REFRESH_VAL, regs + AR71XX_DDR_REG_REFRESH); in ddr_init()
404 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_init()
407 writel(DDR2_TAP_VAL, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_init()
413 void __iomem *regs; in ddr_tap_tuning() local
416 regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE, in ddr_tap_tuning()
419 tap_val = readl(regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
426 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
427 writel(tap, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()
429 writel(DDR_BIST_COMP_CNT(8), regs + DDR_REG_BIST_COMP_ADDR_1); in ddr_tap_tuning()
430 writel(DDR_BIST_MASK_ADDR_VAL, regs + DDR_REG_BIST_MASK_ADDR_0); in ddr_tap_tuning()
431 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_1); in ddr_tap_tuning()
432 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_0); in ddr_tap_tuning()
433 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE1_1); in ddr_tap_tuning()
434 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_0); in ddr_tap_tuning()
435 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE0_1); in ddr_tap_tuning()
436 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_0); in ddr_tap_tuning()
437 writel(0xffff, regs + DDR_REG_BIST_MASK_AHB_GE1_1); in ddr_tap_tuning()
438 writel(0xffff, regs + DDR_REG_BIST_COMP_AHB_GE0_0); in ddr_tap_tuning()
441 writel(DDR_BIST_TEST_START, regs + DDR_REG_BIST); in ddr_tap_tuning()
444 val = readl(regs + DDR_REG_BIST_STATUS); in ddr_tap_tuning()
448 writel(0, regs + DDR_REG_BIST); in ddr_tap_tuning()
469 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL0); in ddr_tap_tuning()
470 writel(tap_val, regs + AR71XX_DDR_REG_TAP_CTRL1); in ddr_tap_tuning()