Lines Matching refs:pregs
118 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar933x() local
132 clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG, in eth_init_ar933x()
153 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_ar934x() local
164 writel(0x570, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in eth_init_ar934x()
166 writel(0x271, pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG); in eth_init_ar934x()
167 writel(BIT(26) | BIT(25), pregs + AR934X_PLL_ETH_XMII_CONTROL_REG); in eth_init_ar934x()
204 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in qca956x_sgmii_cal() local
210 writel(BIT(2) | BIT(0), pregs + QCA956X_PLL_ETH_SGMII_SERDES_REG); in qca956x_sgmii_cal()
249 writel(BIT(2) | BIT(0), pregs + QCA956X_PLL_ETH_SGMII_SERDES_REG); in qca956x_sgmii_cal()
400 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in eth_init_qca956x() local
410 writel(0x45500, pregs + QCA956X_PLL_SWITCH_CLK_CTRL_REG); in eth_init_qca956x()
412 writel(0xc5200, pregs + QCA956X_PLL_SWITCH_CLK_CTRL_REG); in eth_init_qca956x()
420 pregs + QCA956X_PLL_ETH_XMII_CTRL_REG); in eth_init_qca956x()
481 void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE, in usb_reset_qca953x() local
484 clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG, in usb_reset_qca953x()