Lines Matching refs:ddr
305 out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_CLK_CNTL); in dram_init()
306 out_be32(&im->ddr.csbnds[0].csbnds, CFG_SYS_DDR_CS0_BNDS); in dram_init()
307 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); in dram_init()
309 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in dram_init()
310 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in dram_init()
311 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in dram_init()
312 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in dram_init()
313 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in dram_init()
314 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in dram_init()
315 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in dram_init()
316 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in dram_init()
317 out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); in dram_init()
320 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in dram_init()