Lines Matching refs:ddr
45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
46 out_be32(&im->ddr.cs_config[0], CFG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
49 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
51 out_be32(&im->ddr.sdram_clk_cntl, CFG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_3, CFG_SYS_DDR_TIMING_3); in fixed_sdram()
53 out_be32(&im->ddr.timing_cfg_1, CFG_SYS_DDR_TIMING_1); in fixed_sdram()
54 out_be32(&im->ddr.timing_cfg_2, CFG_SYS_DDR_TIMING_2); in fixed_sdram()
55 out_be32(&im->ddr.timing_cfg_0, CFG_SYS_DDR_TIMING_0); in fixed_sdram()
57 out_be32(&im->ddr.sdram_cfg, CFG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
58 out_be32(&im->ddr.sdram_cfg2, CFG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
59 out_be32(&im->ddr.sdram_mode, CFG_SYS_DDR_MODE); in fixed_sdram()
60 out_be32(&im->ddr.sdram_mode2, CFG_SYS_DDR_MODE2); in fixed_sdram()
62 out_be32(&im->ddr.sdram_interval, CFG_SYS_DDR_INTERVAL); in fixed_sdram()
66 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()