Lines Matching refs:debug
79 debug("workaround rows - memsize %lld\n", memsize); in get_errata_rows()
80 debug("workaround rows - cs %d\n", cs); in get_errata_rows()
81 debug("workaround rows - width %d\n", width); in get_errata_rows()
82 debug("workaround rows - rows %d\n", rows); in get_errata_rows()
83 debug("workaround rows - banks %d\n", banks); in get_errata_rows()
84 debug("workaround rows - cols %d\n", cols); in get_errata_rows()
87 debug("rows workaround - term1 %lld\n", newrows); in get_errata_rows()
90 debug("rows workaround - term2 %lld\n", newrows); in get_errata_rows()
99 debug("rows workaround - bits %d\n", bits); in get_errata_rows()
113 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows); in get_errata_rows()
138 debug("sdram set rule start %x, %d\n", lo_addr_bits, in sdram_set_rule()
140 debug("sdram set rule end %x, %d\n", hi_addr_bits, in sdram_set_rule()
234 debug("SDRAM Prot rule, default %x\n", in sdram_dump_protection_config()
240 debug("Rule %d, rules ...\n", rules); in sdram_dump_protection_config()
241 debug(" sdram start %x\n", rule.sdram_start); in sdram_dump_protection_config()
242 debug(" sdram end %x\n", rule.sdram_end); in sdram_dump_protection_config()
243 debug(" low prot id %d, hi prot id %d\n", in sdram_dump_protection_config()
246 debug(" portmask %x\n", rule.portmask); in sdram_dump_protection_config()
247 debug(" security %d\n", rule.security); in sdram_dump_protection_config()
248 debug(" result %d\n", rule.result); in sdram_dump_protection_config()
249 debug(" valid %d\n", rule.valid); in sdram_dump_protection_config()
265 debug(" Write - Address 0x%p Data 0x%08x\n", addr, val); in sdram_write_verify()
268 debug(" Read and verify..."); in sdram_write_verify()
271 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n", in sdram_write_verify()
276 debug("correct!\n"); in sdram_write_verify()
304 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n"); in sdr_get_ctrlcfg()
308 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n"); in sdr_get_ctrlcfg()
351 debug("\nConfiguring CTRLCFG\n"); in sdr_load_regs()
354 debug("Configuring DRAMTIMING1\n"); in sdr_load_regs()
357 debug("Configuring DRAMTIMING2\n"); in sdr_load_regs()
360 debug("Configuring DRAMTIMING3\n"); in sdr_load_regs()
363 debug("Configuring DRAMTIMING4\n"); in sdr_load_regs()
366 debug("Configuring LOWPWRTIMING\n"); in sdr_load_regs()
369 debug("Configuring DRAMADDRW\n"); in sdr_load_regs()
372 debug("Configuring DRAMIFWIDTH\n"); in sdr_load_regs()
375 debug("Configuring DRAMDEVWIDTH\n"); in sdr_load_regs()
378 debug("Configuring LOWPWREQ\n"); in sdr_load_regs()
381 debug("Configuring DRAMINTR\n"); in sdr_load_regs()
384 debug("Configuring STATICCFG\n"); in sdr_load_regs()
387 debug("Configuring CTRLWIDTH\n"); in sdr_load_regs()
390 debug("Configuring PORTCFG\n"); in sdr_load_regs()
393 debug("Configuring FIFOCFG\n"); in sdr_load_regs()
396 debug("Configuring MPPRIORITY\n"); in sdr_load_regs()
399 debug("Configuring MPWEIGHT_MPWEIGHT_0\n"); in sdr_load_regs()
405 debug("Configuring MPPACING_MPPACING_0\n"); in sdr_load_regs()
411 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n"); in sdr_load_regs()
416 debug("Configuring PHYCTRL_PHYCTRL_0\n"); in sdr_load_regs()
419 debug("Configuring CPORTWIDTH\n"); in sdr_load_regs()
422 debug("Configuring CPORTWMAP\n"); in sdr_load_regs()
425 debug("Configuring CPORTRMAP\n"); in sdr_load_regs()
428 debug("Configuring RFIFOCMAP\n"); in sdr_load_regs()
431 debug("Configuring WFIFOCMAP\n"); in sdr_load_regs()
434 debug("Configuring CPORTRDWR\n"); in sdr_load_regs()
437 debug("Configuring DRAMODT\n"); in sdr_load_regs()
441 debug("Configuring EXTRATIME1\n"); in sdr_load_regs()
483 debug("Configuring STATICCFG\n"); in sdram_mmr_init_full()
561 debug("%s returns %ld\n", __func__, temp); in sdram_calculate_size()
598 debug("SDRAM: Calibrating PHY\n"); in altera_gen5_sdram_probe()
606 debug("SDRAM: %ld MiB\n", sdram_size >> 20); in altera_gen5_sdram_probe()