Lines Matching refs:regs
54 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, in fsl_ddr_set_memctl_regs() argument
110 mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK; in fsl_ddr_set_memctl_regs()
116 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
118 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
119 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
121 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); in fsl_ddr_set_memctl_regs()
127 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
129 (regs->cs[i].config & in fsl_ddr_set_memctl_regs()
132 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
133 ddr_out32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
135 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
140 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
142 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
144 ddr_out32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
145 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
150 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
152 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
154 ddr_out32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
155 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
160 (regs->cs[i].bnds & 0xfffefffe) >> 1); in fsl_ddr_set_memctl_regs()
162 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
164 ddr_out32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
165 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); in fsl_ddr_set_memctl_regs()
169 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); in fsl_ddr_set_memctl_regs()
170 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); in fsl_ddr_set_memctl_regs()
171 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
172 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); in fsl_ddr_set_memctl_regs()
173 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); in fsl_ddr_set_memctl_regs()
174 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
175 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6); in fsl_ddr_set_memctl_regs()
176 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); in fsl_ddr_set_memctl_regs()
177 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8); in fsl_ddr_set_memctl_regs()
178 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9); in fsl_ddr_set_memctl_regs()
179 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); in fsl_ddr_set_memctl_regs()
180 ddr_out32(&ddr->dq_map_0, regs->dq_map_0); in fsl_ddr_set_memctl_regs()
181 ddr_out32(&ddr->dq_map_1, regs->dq_map_1); in fsl_ddr_set_memctl_regs()
182 ddr_out32(&ddr->dq_map_2, regs->dq_map_2); in fsl_ddr_set_memctl_regs()
183 ddr_out32(&ddr->dq_map_3, regs->dq_map_3); in fsl_ddr_set_memctl_regs()
184 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); in fsl_ddr_set_memctl_regs()
185 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); in fsl_ddr_set_memctl_regs()
186 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); in fsl_ddr_set_memctl_regs()
187 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); in fsl_ddr_set_memctl_regs()
188 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); in fsl_ddr_set_memctl_regs()
189 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); in fsl_ddr_set_memctl_regs()
190 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); in fsl_ddr_set_memctl_regs()
191 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); in fsl_ddr_set_memctl_regs()
192 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); in fsl_ddr_set_memctl_regs()
193 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9); in fsl_ddr_set_memctl_regs()
194 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10); in fsl_ddr_set_memctl_regs()
195 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11); in fsl_ddr_set_memctl_regs()
196 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12); in fsl_ddr_set_memctl_regs()
197 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13); in fsl_ddr_set_memctl_regs()
198 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14); in fsl_ddr_set_memctl_regs()
199 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15); in fsl_ddr_set_memctl_regs()
200 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16); in fsl_ddr_set_memctl_regs()
201 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); in fsl_ddr_set_memctl_regs()
204 regs->ddr_sdram_interval & ~SDRAM_INTERVAL_BSTOPRE); in fsl_ddr_set_memctl_regs()
206 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()
208 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); in fsl_ddr_set_memctl_regs()
209 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); in fsl_ddr_set_memctl_regs()
216 if (regs->ddr_wrlvl_cntl_2) in fsl_ddr_set_memctl_regs()
217 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); in fsl_ddr_set_memctl_regs()
218 if (regs->ddr_wrlvl_cntl_3) in fsl_ddr_set_memctl_regs()
219 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
222 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); in fsl_ddr_set_memctl_regs()
223 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); in fsl_ddr_set_memctl_regs()
224 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); in fsl_ddr_set_memctl_regs()
225 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3); in fsl_ddr_set_memctl_regs()
226 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4); in fsl_ddr_set_memctl_regs()
227 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); in fsl_ddr_set_memctl_regs()
228 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); in fsl_ddr_set_memctl_regs()
232 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
238 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); in fsl_ddr_set_memctl_regs()
242 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
243 ddr_out32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
244 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); in fsl_ddr_set_memctl_regs()
245 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
250 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in fsl_ddr_set_memctl_regs()
251 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */ in fsl_ddr_set_memctl_regs()
253 regs->ddr_sdram_rcw_2 & ~0xf0); in fsl_ddr_set_memctl_regs()
255 ddr_out32(&ddr->err_disable, regs->err_disable | in fsl_ddr_set_memctl_regs()
259 ddr_out32(&ddr->err_disable, regs->err_disable); in fsl_ddr_set_memctl_regs()
261 ddr_out32(&ddr->err_int_en, regs->err_int_en); in fsl_ddr_set_memctl_regs()
263 if (regs->debug[i]) { in fsl_ddr_set_memctl_regs()
265 i+1, regs->debug[i]); in fsl_ddr_set_memctl_regs()
266 ddr_out32(&ddr->debug[i], regs->debug[i]); in fsl_ddr_set_memctl_regs()
275 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); in fsl_ddr_set_memctl_regs()
286 regs->ddr_cdr2 | DDR_CDR2_VREF_TRAIN_EN); in fsl_ddr_set_memctl_regs()
296 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); in fsl_ddr_set_memctl_regs()
328 temp32 = regs->ddr_sdram_cfg; in fsl_ddr_set_memctl_regs()
379 if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) in fsl_ddr_set_memctl_regs()
384 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) in fsl_ddr_set_memctl_regs()
387 mr6 = (regs->ddr_sdram_mode_10 >> 16) | in fsl_ddr_set_memctl_regs()
428 if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { in fsl_ddr_set_memctl_regs()
430 if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { in fsl_ddr_set_memctl_regs()
432 if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN)) in fsl_ddr_set_memctl_regs()
444 regs->err_disable & ~DDR_ERR_DISABLE_APED); in fsl_ddr_set_memctl_regs()
448 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); in fsl_ddr_set_memctl_regs()
456 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) || in fsl_ddr_set_memctl_regs()
457 IS_DBI(regs->ddr_sdram_cfg_3)) { in fsl_ddr_set_memctl_regs()
496 if (!(regs->cs[i].config & 0x80000000)) in fsl_ddr_set_memctl_regs()
499 ((regs->cs[i].config >> 14) & 0x3) + 2 + in fsl_ddr_set_memctl_regs()
500 ((regs->cs[i].config >> 8) & 0x7) + 12 + in fsl_ddr_set_memctl_regs()
501 ((regs->cs[i].config >> 4) & 0x3) + 0 + in fsl_ddr_set_memctl_regs()
502 ((regs->cs[i].config >> 0) & 0x7) + 8 + in fsl_ddr_set_memctl_regs()
503 ((regs->ddr_sdram_cfg_3 >> 4) & 0x3) + in fsl_ddr_set_memctl_regs()
504 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) - in fsl_ddr_set_memctl_regs()
540 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds); in fsl_ddr_set_memctl_regs()
542 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds); in fsl_ddr_set_memctl_regs()
544 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds); in fsl_ddr_set_memctl_regs()
546 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds); in fsl_ddr_set_memctl_regs()
550 ddr_out32(&ddr->cs0_config, regs->cs[0].config); in fsl_ddr_set_memctl_regs()
554 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); in fsl_ddr_set_memctl_regs()