Lines Matching refs:ddr
32 struct ccsr_ddr __iomem *ddr; in fsl_ddr_get_version() local
37 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_get_version()
41 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_get_version()
46 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_get_version()
51 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_get_version()
58 ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; in fsl_ddr_get_version()
59 ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; in fsl_ddr_get_version()
183 struct ccsr_ddr __iomem *ddr = in print_ddr_info() local
190 uint32_t cs0_config = ddr_in32(&ddr->cs0_config); in print_ddr_info()
192 uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
198 ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR; in print_ddr_info()
199 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
205 ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR; in print_ddr_info()
206 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
243 cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf); in print_ddr_info()
248 cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4; in print_ddr_info()
351 struct ccsr_ddr __iomem *ddr; in fsl_ddr_sync_memctl_refresh() local
356 ddr = (void *)CFG_SYS_FSL_DDR_ADDR; in fsl_ddr_sync_memctl_refresh()
360 ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; in fsl_ddr_sync_memctl_refresh()
365 ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; in fsl_ddr_sync_memctl_refresh()
370 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_sync_memctl_refresh()
377 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()
378 ddrc_debug2_p[i] = &ddr->debug[1]; in fsl_ddr_sync_memctl_refresh()
382 ddrc_debug20 = ddr_in32(&ddr->debug[19]); in fsl_ddr_sync_memctl_refresh()
384 ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; in fsl_ddr_sync_memctl_refresh()