Lines Matching refs:idx
343 int idx; in overrun() local
345 idx = pup + ecc * ECC_BIT; in overrun()
348 if (info->rl_val[cs][idx][S] == RL_UNLOCK_STATE) { in overrun()
351 if (info->rl_val[cs][idx][C] < RL_RETRY_COUNT) { in overrun()
354 info->rl_val[cs][idx][C]++; in overrun()
357 if (info->rl_val[cs][idx][C] == RL_RETRY_COUNT) { in overrun()
358 info->rl_val[cs][idx][C] = 0; in overrun()
359 info->rl_val[cs][idx][DS] = delay; in overrun()
360 info->rl_val[cs][idx][PS] = phase; in overrun()
363 info->rl_val[cs][idx][S] = RL_FINAL_STATE; in overrun()
513 int idx; in ddr3_read_leveling_single_cs_rl_mode() local
515 idx = pup + ecc * ECC_BIT; in ddr3_read_leveling_single_cs_rl_mode()
579 if (dram_info->rl_val[cs][idx][S] in ddr3_read_leveling_single_cs_rl_mode()
608 rl_val[cs][idx][S] == 0) { in ddr3_read_leveling_single_cs_rl_mode()
681 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_rl_mode()
682 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_rl_mode()
823 int idx; in ddr3_read_leveling_single_cs_window_mode() local
825 idx = pup + ecc * ECC_BIT; in ddr3_read_leveling_single_cs_window_mode()
834 if (dram_info->rl_val[cs][idx][S] == RL_WINDOW_STATE) { in ddr3_read_leveling_single_cs_window_mode()
847 dram_info->rl_val[cs][idx][DE] = delay; in ddr3_read_leveling_single_cs_window_mode()
848 dram_info->rl_val[cs][idx][PE] = phase; in ddr3_read_leveling_single_cs_window_mode()
850 dram_info->rl_val[cs][idx][S]++; in ddr3_read_leveling_single_cs_window_mode()
857 } else if (dram_info->rl_val[cs][idx][S] == in ddr3_read_leveling_single_cs_window_mode()
864 if (dram_info->rl_val[cs][idx][C] < in ddr3_read_leveling_single_cs_window_mode()
870 dram_info->rl_val[cs][idx][C]++; in ddr3_read_leveling_single_cs_window_mode()
873 if (dram_info->rl_val[cs][idx][C] == in ddr3_read_leveling_single_cs_window_mode()
875 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
876 dram_info->rl_val[cs][idx][DS] = in ddr3_read_leveling_single_cs_window_mode()
878 dram_info->rl_val[cs][idx][PS] = in ddr3_read_leveling_single_cs_window_mode()
880 dram_info->rl_val[cs][idx][S]++; /* Go to Window State */ in ddr3_read_leveling_single_cs_window_mode()
1084 if (dram_info->rl_val[cs][idx][C] < RL_RETRY_COUNT) in ddr3_read_leveling_single_cs_window_mode()
1085 dram_info->rl_val[cs][idx][C] = 0; in ddr3_read_leveling_single_cs_window_mode()
1111 if (dram_info->rl_val[cs][idx][PS] == 4) in ddr3_read_leveling_single_cs_window_mode()
1112 dram_info->rl_val[cs][idx][PS] = 1; in ddr3_read_leveling_single_cs_window_mode()
1113 if (dram_info->rl_val[cs][idx][PE] == 4) in ddr3_read_leveling_single_cs_window_mode()
1114 dram_info->rl_val[cs][idx][PE] = 1; in ddr3_read_leveling_single_cs_window_mode()
1116 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1117 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1118 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1119 MAX_DELAY_INV + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1129 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1130 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY_INV; in ddr3_read_leveling_single_cs_window_mode()
1133 delay_s = dram_info->rl_val[cs][idx][PS] * in ddr3_read_leveling_single_cs_window_mode()
1134 MAX_DELAY + dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1135 delay_e = dram_info->rl_val[cs][idx][PE] * in ddr3_read_leveling_single_cs_window_mode()
1136 MAX_DELAY + dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1144 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1145 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()
1149 if (dram_info->rl_val[cs][idx][PS] > 1) in ddr3_read_leveling_single_cs_window_mode()
1150 dram_info->rl_val[cs][idx][PS] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1151 if (dram_info->rl_val[cs][idx][PE] > 1) in ddr3_read_leveling_single_cs_window_mode()
1152 dram_info->rl_val[cs][idx][PE] -= 2; in ddr3_read_leveling_single_cs_window_mode()
1155 delay_s = dram_info->rl_val[cs][idx][PS] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1156 dram_info->rl_val[cs][idx][DS]; in ddr3_read_leveling_single_cs_window_mode()
1157 delay_e = dram_info->rl_val[cs][idx][PE] * MAX_DELAY + in ddr3_read_leveling_single_cs_window_mode()
1158 dram_info->rl_val[cs][idx][DE]; in ddr3_read_leveling_single_cs_window_mode()
1168 dram_info->rl_val[cs][idx][P] = phase; in ddr3_read_leveling_single_cs_window_mode()
1169 dram_info->rl_val[cs][idx][D] = tmp % MAX_DELAY; in ddr3_read_leveling_single_cs_window_mode()